How to design a better 1.5-V 2.4-GHz CMOS PLL for wireless applications
Mingliang Liu, Lava Technologies
Feb 21, 2006 (2:05 PM), CommsDesign
Since the VCO is one of the most important elements in the PLL system it is an appropriate place to begin this article, which addresses the challenges of designing a 1.5-V 2.4-GHz CMOS Phase Locked Loop (PLL) for wireless LAN applications. The design assumes a specific process, namely TSMC 0.35 micron technology.
The schematic of the VCO is shown in Figure 1. Transistors M8 and M9 form a NMOS cross-coupled differential pair to provide the negative resistance, which is required for generating an oscillation. M0, M1 and R3 form the biasing network for the oscillator. L7 and C8 form the filtering network to suppress the high frequency noise generated by the bias current source.
Related Semiconductor IP
- NPU IP Core for Mobile
- MSP7-32 MACsec IP core for FPGA or ASIC
- UHF RFID tag IP with 3.6kBit EEPROM and -18dBm sensitivity
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
Related White Papers
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
- It's Not My Fault! How to Run a Better Fault Campaign Using Formal
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity