How to build a self-checking testbench
William Kafig, Xilinx
EETimes (2/17/2012 7:15 AM EST)
A testbench, as it’s known in VHDL, or a test fixture in Verilog, is a construct that exists in a simulation environment such as ISim, ModelSim or NCsim. Simulation enables a unit under test (UUT) – typically, your synthesizable FPGA design – to connect to virtual (simulated) components such as memory, communication devices and/or CPUs, and be driven with a known set of stimuli. These stimuli cause the UUT to react and interact with the virtual components. You can view both the stimulus and the reaction as waveforms in the simulation environment.
Here’s quick example to illustrate how to implement a testbench using a simple 8-bit up/down with reset as the FPGA design (UUT). The testbench provides clock, up/down, enable and reset control signals. Figure 1 shows how to connect the UUT (central gray box) to a testbench.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- MSP7-32 MACsec IP core for FPGA or ASIC
- UHF RFID tag IP with 3.6kBit EEPROM and -18dBm sensitivity
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
Related White Papers
- It's Not My Fault! How to Run a Better Fault Campaign Using Formal
- How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it
- Four ways to build a CAD flow: In-house design to custom-EDA tool
- How to build a fast, custom FFT from C
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity