Four ways to build a CAD flow: In-house design to custom-EDA tool
By Daniel Hoggar, Verific Design Automation
EDN (June 9, 2022)
An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.
And yet, every semiconductor project group deals with inefficiencies that constrain them from delivering ideal solutions and limits productivity. Today’s CAD engineers use a patchwork of tools, flows and scripts consisting of commercial electronic design automation (EDA) products, commercial or in-house customized add-ons and in-house intellectual property (IP), a problem for many project groups because of:
- Tool flow gaps in existing EDA products
- The burden of maintaining in-house or homegrown tools, flows and scripts
- The lack of time to build and test high-quality, robust internal tools
That inevitably leads to a bunch of problems, as explained in the following sections.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- Exploring a Parallel Universe - It's Coming to a Design Near You
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
- Vital Ways to Prevent a Cyberattack
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience