Building a NAND flash controller with high-level synthesis

Tung-Hua Yeh and Jen-Chieh Yeh, Industrial Technology Research Institute; and Qiang Zhu, Cadence Design Systems
EETimes (3/19/2012 3:18 PM EDT)

High-level synthesis (HLS) is a key technology that links electronic system-level (ESL) design to register transfer-level (RTL) implementation. In addition to automating the ESL-to-RTL design flow, HLS enables efficient design space exploration that helps designers quickly achieve a micro-architecture that meets their goals. However, traditional HLS technologies were mainly applicable only to datapath-dominated design and were not effective for control-intensive design. Also, traditional HLS technologies required specific design styles and use models to achieve good quality of results (QoR).

In this article, we describe how we were able to apply a commercial HLS tool (Cadence C-to-Silicon Compiler) to a NAND flash controller with an error correction code (ECC) block. The initial ECC design was based on an ECC software program, which led to a large area due to two large arrays. We then used our domain knowledge of the ECC coding theorem to structure the code for hardware implementation. The implemented results show that (1) the HLS tool can achieve QoR comparable to handwritten RTL for a control-intensive design; (2) a design flow that properly considers the hardware implementation is a key factor in achieving good QoR in an HLS flow; and (3) an HLS flow gains a factor of two design productivity compared to an RTL flow.

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