Analogue heaven

Analogue heaven
By Nick Flaherty, EE Times UK
February 12, 2002 (6:50 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020211S0085

While the world of analogue design is very different to that of digital, it is still vital to the development of complex systems, from data converters and clock generators to power converters.

The sector has taken a different road to system-on-chip integration, and analogue designers still have issues with the increasing complexity of the simulation models and the hardware to run them. The analogue design groups at Texas Instruments' (TI) centre of excellence for analogue design in Freising, Germany, have been developing methodologies for designing analogue and mixed-signal components.

The site currently employs more than 1200 people and includes TI's main BiCMOS wafer fab, which is also used for some of the analogue products that are not suited to CMOS processes. The low-power DC/DC converters designed on the site still use a bipolar process for the operational amplifiers with very low offset and voltage references.

Uwe Mengelkamp, TI's wo rldwide director for low- power DC/DC products, said: "These involve currents of 100mA combined with power devices that switch currents up to one or two amps — it's a completely different problem from high-frequency design."

Communal design support

Despite being focused on analogue design, the design teams follow a similar split. Werner Elmer, 1394 PHY design manager and a member of TI's technical staff, said: "We have one communal design support organisation for all the design groups so that our designers use similar tools and similar design flows.

"For digital, we use a standard asic flow and import the analogue blocks. So for something more digital like a 1394, we would import the physical design into the larger asic part, which is several hundred thousand gates. For the analogue flow, such as an I2C bus controller, then we synthesise the digital part with standard asic design tools and then import it into the analogue layout."

For pure analogue desig n, such as phase-locked loops, the design group uses MathCAD to test loop parameters and fit them to the requirements. But it is the physical part of the design that is key to the analogue development. This is a complex mixture of high-level language description of the design with analogue Verilog and transistor-level design using Spice simulation.

Eckart M&uumlaut;ller, TI's design manager for the power management products, said: "We have a library of top-level models in MathCAD to give us a rough idea of what parameters to design for, for example to set up the switching algorithms. The main issue we have to address is simulation time.

"Previous simulation was done with Spice, and we need the Spice model capability because it gives the greatest accuracy, but the simulation times are very long at the top level. So we started to replace parts of the modelling with Verilog Analog.

"Some problems are very detailed, such as coupling capacitors between blocks, and we can't get rid of th e transistor simulation — we have to simulate the whole thing in Spice. But it opens up a whole range of opportunities for adding functions."

Most of the converters operate in different modes, but there is also a skip mode for low loads currents or for maintaining the voltage. This allows the converter to work when the voltage falls beyond a certain level and bring up the voltage. This provides maximum efficiency for the whole system as well as the transistor.

Mengelkamp believes that the name of the game is efficiency: "A 5% difference means a lot to the customer base as it translates into hours of battery life."

Reuse is at an even higher level, says Kevin Spooner, analogue design engineer and a senior member of the technical staff. "In circuit design, we might take a basic circuit and modify transistor designs. That happens most of the time, so we have a lot of reuse in ideas and architectures," he said.

The basic design flow is TI's own simulator, TI-Spice, integrated with Cadence Design Systems' design tool environment with the K2 verification tool from Synopsys. The key Spice models are created in Dallas by a dedicated team.

"TI-Spice is faster than commercial products and works fine, so it's no sweat," said Elmer. "We are always looking to trade off accuracy and simulation time so, for top-level simulation, we are using PowerMill which works well but the accuracy is low."

This tool predicts power consumption, explores alternatives for minimising power, budgets power, identifies budget violations and pinpoints where and how excessive power is consumed so that designs can be optimised.

But the designers are being held back by the hardware, say both Eckart and M&uumlaut;ller.

"We spend the same time on simulation as we did 10 years ago," said Elmer. "That's why we use Verilog analogue to speed up the system simulations." This is not just a result of the increase in complexity but a need for more simulati on of factors such as para-sitics, says M&uumlaut;ller: "It's not only the chip complexity that goes up — the models are getting better and the production is getting better so you have to do more and more to the parasitic performance."

This is driving more focus on back-annotation. They are using standard back-annotation tools and have lot of expertise in house, but that also increases the simulation time.

"Critical passes are back-annotated 100%, but the rest we leave off," said M&uumlaut;ller. "What we really need is a tool that allows us to attach the pins to the circuits that we want to back-annotate to get more ease of use in the process." There are also issues of simulation and modelling of the packaging, particularly at high frequencies, he says. "What our designers want is an electrically neutral package."

Performance ruined

A group in Dallas extracts models for the lead inductance, capacitor ground, mutual capacitance, mutual indu ctance and length of bond wire. "This is even more important with higher frequencies and higher drive currents, and if you have both, it's extremely important and can ruin your performance," he said.

But this changes with each design. Elmer said: "We require a package model specific for the IC because it depends where the bond pads are, and we also use it to make decisions on pinout and pin placement."

So even with all the tools and the design flow, handcrafting the designs is required in some circumstances.

"Sometimes we have to simulate the environment such as the specific noise sources and use a filter mechanism to filter that out," said Elmer. "This leads to a handcrafted model and it can be a killer, but it's not the rule."