Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)
Graham LS Connolly, Principal Engineer, and Tony Lee, Applications Engineer, Fairchild Semiconductor Corp.
3/16/2011 1:08 PM EDT
(Part 1 looked at the nature of the problem, as well as the requirements of D-PHY MIPI® dual camera/dual display applications, click here to read it.)
What is the solution?
The solution is to add an analog switch.
When inserting an analog switch, the key influencing factor is still the incident wave response, as the switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate good âeyeâ performance by minimizing reflections and edge rate degradation. Initially, the extra CON/COFF of the switch may be viewed as a detriment to the system performance, but in reality, removing the discontinuity reflections outweighs the extra capacitance and series resistance incurred by inserting the analog switch. The MIPI specifications use a 0.3 UI (unit interval) for the criteria of Interoperability, so the faster you want to run your system, the more critical the switch CON/COFF characteristics becomes, since that is the parameter that will impact the edge rate and, therefore, the 0.3 UI criteria.
To read the full article, click here
Related Semiconductor IP
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
Related White Papers
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2)
- All you need to know about MIPI D-PHY RX
- A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY
- Demystifying MIPI C-PHY / DPHY Subsystem
Latest White Papers
- Boosting RISC-V SoC performance for AI and ML applications
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU