When Is Verification Done?

Ed Sperling, Semiconductor Engineering
December 20, 2013

Reaching a sufficient confidence level that SoC designs will work as designed is becoming much harder.

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification.

The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debugging process keeps turning up new bugs as SoCs are rolled out. Some of them can be fixed in software, some of them can be fixed in the next rev of a chip—often a re-spin of a pre-production chip—but some of them also make their way out into the market where they can cause havoc. And it’s not just the hardware that has to be verified anymore.