VLSI Solution releases an Ultra Low power Multiprocessor DSP core
Tampere, Finland, 19 March 2002 – VLSI Solution has announced the second generation of its ultra low power VS_DSP core processor.
VS_DSP 4 has the following major improvements over the old VS_DSP core:
• Double operation frequency
• Floating-point arithmetic requires half of the clock cycles (4x speed-up)
• Rounding instruction speeds up digital filtering
• Faster external memory access
• No power consumption penalty due to additional features
• No gate count penalty due to additional features
• C-level debugger added to the software tool set
• Multi-core support added to the software tools
A three-processor VS_DSP 4 cluster that provides 600 million MAC instructions per second requires less than 1 mm 2 silicon area in 0.18 µm technology and uses less than 30 mA (<50 µA/MHz/processor).
The software development kit is immediately available. The figure below shows the evaluation board for 3G portable platform with three processors, configurable logic and high-speed analog.
Like its predecessors, VS_DSP 4 is available as a VHDL soft core for licensing or as a building block for design service and manufacturing projects of VLSI Solution.
“The new processor makes it possible to implement cost and power effectively new real-time algorithms, such as MP3 encoding. Our symmetric parallel engine makes software development of parallel processors straightforward”, says Tapani Ritoniemi, Managing Director of VLSI Solution.
Related Semiconductor IP
Related News
- Cadence Introduces the Voltus-XFi Custom Power Integrity Solution, Delivering over 3X Productivity Gains
- Diakopto Unveils PrimeX™ - Revolutionary EDA Solution for Top-Hierarchy Power Grid and Signal Net EM/IR
- Samsung Foundry Certifies Cadence Voltus-XFi Custom Power Integrity Solution for 5LPE Process Technology
- DSP Concepts and Analog Devices Collaborate on Solution for Rapid Design of In-Vehicle Audio Entertainment Systems
Latest News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- TSMC shuns high-NA EUV lithography
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Weebit Nano Q3 FY25 Quarterly Activities Report
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications