Virage Logic Standardizes on Synopsys' ESP for Memory Verification
MOUNTAIN VIEW, Calif., February 28, 2005 – Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced that Virage Logic Corporation (Nasdaq:VIRL), a leading provider of semiconductor IP platforms, has standardized on Synopsys’ ESP memory equivalency checker for the embedded memory components of its IPrima™ Mobile semiconductor IP platform. ESP’s unique symbolic simulation capabilities improve verification productivity by at least 2X over previous approaches. The increase in productivity enabled Virage Logic to trim the engineering time needed to complete functional verification of the circuits in its Area, Speed and Power (ASAP) Memory™ compilers from days to hours.
"ESP has a solid track record at Virage Logic, and we’re now standardizing on it to verify the simulation models for our memories directly against the SPICE netlists," said Alex Shubat, chief technology officer and vice president of research and development at Virage Logic. "ESP provides a tremendous productivity boost to our verification team, enabling them to complete functional verification with less effort. In addition, ESP helps us debug the functionality in our models."
ESP is an equivalency checker for memories that compares a Verilog simulation model directly to an HSPICE® netlist. Its patented application of symbolic simulation and formal proof engines enables the functional verification of full-custom memories, macros and libraries used in today's complex ICs. ESP is ideally suited for verifying embedded memories in system-on-chip (SoC) designs.
"Virage Logic has long been a leader in providing differentiated embedded memory IP to the world’s leading foundries, integrated device manufacturers and fabless customers worldwide," said Bijan Kiani, vice president of marketing at Synopsys. "Their standardization on ESP for memory IP is another example of ESP’s ability to boost productivity and reduce time-to-results for memory verification."
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.
Synopsys and HSPICE are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
- CAN-FD Controller
Related News
- Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
- Synopsys Expands the Industry's Highest Performance Hardware-Assisted Verification Portfolio to Propel Next-Generation Semiconductor and Design Innovation
- PGC Strengthens Cloud and AI ASIC Acceleration with Synopsys’ Next-Generation Interface and Memory IP on Advanced Nodes
Latest News
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP