USB 3.1 Device & Host Controller IP Cores with highly configurable design for Superspeed data transfers in all kinds of advanced SoCs is available for immediate licensing

February 28, 2022 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s USB-IF compliant USB 3.1 Device and Host Controller IP Cores with matching USB 3.1 PHY IP Cores which are silicon proven in major Fabs and Nodes.

USB 3.1 Host and Device Controllers are highly configurable IP Cores that can be interfaced with any third-party USB 3.1 PHY IP Core. The Controller IP Cores are compliant with USB3.1 specification and are architected to include a High-Performance DMA Engine based on xHCI Specification. These IP Cores can be configured to support full-fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chipsets or be configured with a subset of features for embedded applications requiring limited host functionality.

USB 3.1 Host Controller IP exposes either a AXI or AHB Master Interface for the Datapath and an AHB Slave Interface for Register Access. USB 3.1 Host Controller IP Core can be configured to support all types of USB transfers – Bulk, Interrupt and Isochronous and allows dynamic configuration to support configurable number of endpoints, interfaces, alternate interfaces, and configurations. USB 3.1 Host Controller IP Cores can be configured to support any combinations of USB 3.1 interface speeds – SSP (10 Gbps), SS(5 Gbps), HS (480 Mbps), FS(12 Mbps) and LS(1.5 Mbps) with support for all low power features of the USB Specification supporting Suspend and Remote Wakeup.

The USB 3.1 Device Controller IP core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. This controller has a very simple application interface which can be easily adapted to standard on-chip-bus interface. The USB 3.1 Device Controller IP Core implements an aggressive Low Power Management and configurable system clock frequency. Its Layered architecture allows for Bulk Streaming. It also boasts configurable PIPE Interface: 8, 16, 32 bit with optional support for Type-C connectors.

The USB 3.1 Host and Device Controller IP Cores has been silicon proven in Graphics Controller, Flash Storage Controllers, SATA Bridges with support for Bulk Streaming, Embedded Hosts, Docking Stations, Mobile Application Processors, Smart TV, Hubs.

In addition to USB 3.1 Host and Device Controller and PHY IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB OTG, PCIe, HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA, and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com