Availability of Dolphin Integration's TSMC-sponsored ROM at the 130 nm BCD 5 V process
Grenoble, France -- June 21, 2013 -- The growing demand for BCD technology aims at facilitating the integration of logic and analog with relatively high-voltage features on the same SoC for such volume applications where 5 V is due to the USB standard, enabling embedded power regulators with chargers, as well as higher sound power of Audio DACs. Moving to the 130 nm process helps further reduce both cost of silicon area and of BoM for devices on the printed circuit board.
The need for programmable power management networks with embedded MCUs benefits from Dolphin Integration’s portfolio of densest ROM generators, with patented bit-cell optimizations. The company today announces the availability of the silicon proven CASSIOPEIA generator for metal programmable ROM, at the TSMC 130 BCD 5V process.
“We are happy to announce that the ROM CASSIOPEIA generator is now available free of license fees, for all TSMC 130 nm BCD users. This product is tuned to meet the requirements of SoCs embedding Power Management Networks”, said Elsa BERNARD-MOULIN, Marketing Manager at Dolphin Integration.
The ROM CASSIOPEIA significantly reduces power consumption
- A 50% gain in consumption power has been proven compared to usual ROM from contenders.
- CASSIOPEIA optionally features the capability to operate at low voltage, down to 1.2 V +/- 10%: 40% power reduction compared to nominal voltage operation at 1.5 V +/-10%.
Benchmark results have also demonstrated that this Via 1 programmable ROM achieves an average of 20% gain in density compared to other solutions.
The ROM CASSIOPEIA has now passed the pre-silicon assessment criteria (level 1) of TSMC’s stringent IP9000 qualification program. The product is already implemented in many mass production designs in other 130 nm process variants.
Dolphin Integration offers a complete panoply for the TSMC 130 nm BCD process including a 6-Track standard cell library but also RAM and ROM memory generators.
Find out more information about this product on the Presentation Sheet or contact Dolphin’s Library Marketing Manager at ragtime@dolphin.fr.
To request a free access to the FE generator for evaluation purpose or to the BE generator for integration, please click here.
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. Such diverse experience in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.
Related Semiconductor IP
- Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process FF/P
- Silterra 0.11um ULL Single-Port/Dual-Port SRAM, Single-Port Register File and Via ROM Compiler
- Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process FF/P
- Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k
- Metal Programmable ROM Compiler with Row/Column Redundancy Option, supports process G/LV
Related News
- SkyWater Announces Availability of Cadence Open-Source PDK and Reference Design for SkyWater's 130 nm Process
- eMemory Collaborates with Renesas on the Development of its Pure 5V OTP IP Using 130nm BCD Plus Process for Automotive Applications
- Weebit Nano and DB HiTek tape-out ReRAM module in DB HiTek's 130nm BCD process
- Dolphin Integration complements its 130 nm catalog with a low voltage release of the ROM Cassiopeia
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers