TSMC Creates Design Options for New 3nm Node
By Alan Patterson, EETimes (June 22, 2022)
Taiwan Semiconductor Manufacturing Co. (TSMC) has created versions of its upcoming 3nm FinFET node that’s ramping up later this year, allowing chip designers to enhance performance, power efficiency, and transistor density — or select a balance of those options.
TSMC’s 3nm technology, starting production later in 2022, will feature the company’s FinFlex architecture offering choices of standard cells with a 3–2 fin configuration for performance, a 2–1 fin configuration for power efficiency and transistor density, or a 2–2 fin configuration for efficient performance.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- TSMC CLN3FFP HBM4 PHY
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
Related News
- A closer look at TSMC's 3-nm node and FinFlex technology
- TSMC Expansion in Arizona to Target 3-nm Node
- Sofics releases its ESD technology on TSMC 3nm process
- Alphawave Semi Launches Industry's First 3nm UCIe IP with TSMC CoWoS Packaging
Latest News
- IntoPIX & Altera Unlock New Levels Of Efficiency For JPEG XS On Agilex At IBC 2025
- Perceptia Begins Port of pPLL03 to Samsung 8nm Process Technology
- Efinix® Doubles Titanium Product Line
- SmartSoC Solutions Partners with Cortus to Advance Chip Design and Manufacturing for SIM Cards, Smart Cards, Banking Cards, and E-Passports in India
- Fraunhofer IIS and ARRI announce partnership for post-production workflows at IBC 2025