Toshiba, Sony unveil 65-nm embedded memory process

Toshiba, Sony unveil 65-nm embedded memory process
By Mark LaPedus, Semiconductor Business News
December 5, 2002 (1:00 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021202S0091

TOKYO--Enabling the shift towards “ubiquitous computing,” Japan's Toshiba Corp. and Sony Corp. late Monday announced the world's first 65-nm CMOS process technology for embedded memories.

The process technology will enable single-chip devices, said to be one-fourth the size of current embedded chips in the market. The process also enables a 30-nm transistor with the world's fastest switching speeds, as well as the world's smallest cell for embedded DRAM and SRAM.

Toshiba and Sony have utilized 65-nm process to fabricate an embedded DRAM with a cell size of 0.11um2, which will enable a 256-megabit memory to be integrated on a single chip. It also fabricated the world's smallest embedded SRAM cell of only 0.6um2.

The technology will bring the market towards what the companies call “ubiquitous computing,” that is, total connectivity at all times, according to Toshiba and Sony.

The new process technology is the result of a joint developm ent of 90- and 65-nm CMOS processes, which was initiated in May 2001 (see May 18, 2001 story ). Full details will be presented at the International Electron Devices Meeting (IEDM) in San Francisco from Dec. 9-11.

In a release issued late Monday, the companies described some of the details of the process, including the development of a high-performance transistor with a 30-nm gate length.

Fabricated with 193-nm lithography tools and phase-shift photomasks, the transistor is said to have switching speeds of 0.72-ps for NMOSFET and 1.41-ps for PMOSFET at 0.85-Volt (Ioff=100nA/um).

The transistor makes use of a nitrogen concentration plasma nitrided, oxide-gate dielectrics to suppress gate leakage current. This optimization reduces leakage current approximately 50 times more efficiently than conventional silicon dioxide film and allows formation of an oxide with an effective thickness of only 1-nm.

To reduce wiring propagat ion delay and power dissipation, a low-k dielectric material is adopted. The target effective dielectric constant of the interlayer dielectric is around 2.7.