Tensilica vs. Ceva in imaging/vision IP core battle
Junko Yoshida, EETimes
2/12/2013 5:01 AM EST
NEW YORK--Rapidly evolving imaging and embedded vision algorithms are opening up a new battleground for DSP core IP companies in the high-performance and power-efficient imaging needs of mobile handsets, automotive and video products.
Following Ceva’s introduction a year ago of MM3101, a programmable, low-power imaging and vision platform, Tensilica Tuesday (Feb. 12) rolled out an imaging and video dataplane processor unit (DPU), called IVP.
To read the full article, click here
Related Semiconductor IP
Related News
- Digital Blocks DB9000 Display Controller IP Core Family Extends Leadership in 8K, Automotive, Medical, Aerospace, and Industrial SoC Designs
- Freescale vs. TI: Base station SoC battle
- Sensory TrulySecure Face Authentication Software Now Available on Cadence Tensilica Imaging/Vision DSPs
- Morpho's MovieSolid and Morpho Video WDR Now Available on Cadence Tensilica Imaging/Vision DSPs
Latest News
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs
- Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions