System-on-a-Chip Complexity Drives Fujitsu to Adopt Cadence Synthesis Tool
IP News
System-on-a-Chip Complexity Drives Fujitsu to Adopt Cadence Synthesis Tool
SAN JOSE, Calif.----Dec. 8, 1999-- Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced that Fujitsu will provide library support for the Cadence high-capacity, high-performance Envisia(TM) Ambit synthesis tool, which allows rapid synthesis of large, multimillion gate system-on-a-chip (SOC) designs.
Several application specific integrated circuit (ASIC) vendors, including Fujitsu, have seen a rapid increase in demand for the Envisia Ambit synthesis libraries. ``Envisia Ambit synthesis, as a part of our current timing-driven design flow, addresses overall system LSI design efficiencies,'' commented Shigeru Fujii, general manager, System LSI & ASIC Division, Semiconductor Group, Fujitsu. ``We will support 0.35-micron, 0.25-micron, and 0.18-micron libraries and we are working to integrate the Envisia Ambit synthesis flow into our next-generation design environment, IPSymphony.''
This move by Fujitsu will enable its customers to take advantage of the Envisia Ambit synthesis tool's exceptional performance. Multiple design groups within Fujitsu use Envisia Ambit for their production designs. Fujitsu Telecom recently synthesized a 1 million-gate design with superior timing, area, and dramatic runtime improvements using the Envisia tool. ``We are extremely pleased to receive this endorsement from a world-leading company like Fujitsu. Fujitsu's decision to adopt Envisia Ambit synthesis aligns with our technology strategy and creates a baseline to expand to physically knowledgeable synthesis (PKS) for solving advance timing closure and capacity challenges of deep sub-micron system LSI designs,'' said Kiyotaka Fujii, president of Cadence Design Systems, Japan.
Envisia Ambit Synthesis
Envisia Ambit synthesis enables customers to synthesize multi-million-gate designs rapidly with superior results. Envisia Ambit synthesis also has a built-in, high-capacity, high-performance timing analysis tool that enables productive timing closure. The distributed synthesis feature built into Envisia Ambit synthesis leverages modern networked compute environments to dramatically reduce synthesis runtime for large designs. Envisia synthesis with PKS technology, is a revolutionary synthesis product that brings physical timing accuracy to synthesis. With physical accuracy in synthesis, timing closure iterations between synthesis and place-and-route are eliminated resulting in greater productivity and denser, higher performance circuits.
Pricing and Availability
Libraries supporting use of the Ambit synthesis product for the Fujitsu 0.35-micron and 0.25-micron process will be available in December 1999. Libraries supporting the Fujitsu 0.18-micron process will be available starting March 2000. The Cadence Envisia Ambit synthesis tools are available for UNIX-based workstations from Sun Microsystems and Hewlett-Packard.
Envisia Ambit synthesis is offered at an U.S. list price of $25,000 and Envisia Ambit synthesis with PKS is offered at an U.S. list price of $250,000. For information on international pricing, please contact the local Cadence sales office.
About Cadence
Cadence is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.
Note to Editors: Cadence and the Cadence logo are registered trademarks and Envisia is a trademark of Cadence Design Systems, Inc. All other trademarks are the properties of their owners.
Contact:
Cadence Design Systems, Inc.
Deborah Chalmers, 408/428-5795
debc@cadence.com
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
Related News
- Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity
- Design complexity drives need for ESL
- Bluespec High-Level Synthesis Toolset is Selected by Fujitsu
- Forte Design Systems' SystemC High-Level Synthesis Selected for Fujitsu Semiconductor's ASIC Reference Flow
Latest News
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development
- VSORA and GUC Partner on Jotunn8 Datacenter AI Inference Processor
- Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
- GlobalFoundries and Navitas Semiconductor Partner to Accelerate U.S. GaN Technology and Manufacturing for AI Datacenters and Critical Power Applications
- VLSI EXPERT selects Innatera Spiking Neural Processors to build industry-led neuromorphic talent pool