Startup takes dual IP, ESL role
(07/17/2006 9:01 AM EDT)
SANTA CRUZ, Calif.
— CebaTech Inc., launched in 2004 by a group of chip designers who had developed high-level compilation technology for their own needs, this week will announce plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
CebaTech (Eatontown, N.J.) was started by designers who had developed a behavioral Verilog-to-RTL compiler at Sandgate Technologies in 2000. At that time, Tim Sullivan, former general manager of Lucent's optical area networking division, contracted with the Sandgate engineers to build a 1-Gbyte transport offload engine. Sullivan later joined up with three former Sandgate engineers to launch CebaTech, which he heads as president and CEO.
CebaTech today is expected to divulge plans to offer a tool that can compile C-language descriptions in- to synthesizable register-transfer-level code, as well as compile untimed C into cycle-accurate C models. The company claims to support an electronic system-level (ESL) design methodology that allows an entire system-on-chip to be coded in C and to run in a native C software environment where the cycle-accurate model precisely represents the behavior of the generated RTL.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Wipro-NewLogic announces Dual Role Device MAC IP Core based on Certified Wireless USB Technology
- Wipro-NewLogic and Alereon Demonstrate Wireless USB Dual Role Device Solution
- Mentor Graphics Vista ESL Platform Takes Center Stage in Mentor's ESL Strategy with Expanded Functionality
- Innovative Logic Announced Licensing of Their USB3.1 SuperSpeedPlus Dual Role IP
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack