Simply RISC ships the S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor released by Sun Microsystems
Sep 14, 2006 -- Simply RISC has shipped the S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor released by Sun Microsystems few months ago.
The S1 Core is released under the same license of the T1, the GNU General Public License (GPL); the design is freely downloadable from the Simply RISC website at www.srisc.com and no registration is required.
One of the main purposes of Simply RISC was to keep the S1 Core environment as simple as possible to encourage developers: most of the simulation and synthesis activities are now performed with simple push-button scripts and system requirements are very easy to meet.
The environment can run on any Unix/Linux box and no commercial tools are required, since both simulation and synthesis of the Verilog files of the design can be performed using the free software Icarus Verilog.
Due to its Wishbone-compliant bus interface the S1 Core can be easily interconnected to several cores freely available on OpenCores.org to build up a System-on-a-Chip.
Due to the collaborative nature of the GPL license Simply RISC plans to add new features to the S1 Core and test them extensively over the next months with the help of the community.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor, easily synthesized for Virtex-4
- S1 Core updated to OpenSPARC T1 version 1.5
- Sun Microsystems Launches OpenSPARC Project - Ignites New Open Source Community for Breakthrough UltraSPARC T1 Processor
- Sun Accelerates OpenSPARC With the Creation of an Independent OpenSPARC Advisory Board, Support of New Linux Distribution and the First Microprocessor Derivative
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack