Semidynamics: The landscape for RISC-V and AI compute
An interview with Semidynamics CEO Roger Espasa.
By David Harold, Jon Peddie Research (February 24, 2025)
Semidynamics CEO Roger Espasa discusses the company’s high-performance, configurable RISC-V IP, which emphasizes memory bandwidth and customization for AI and HPC. He highlights their Gazzillion Misses latency-handling IP, integrated tensor units, and focus on real-world performance over benchmarks. Espasa sees RISC-V gaining ground on Arm, balancing standardization with flexibility, and predicts a shift in AI and chiplet adoption.
Semidynamics CEO Roger Espasa discusses the company’s high-performance, configurable RISC-V IP, which emphasizes memory bandwidth and customization for AI and HPC. He highlights their Gazzillion Misses latency-handling IP, integrated tensor units, and focus on real-world performance over benchmarks. Espasa sees RISC-V gaining ground on Arm, balancing standardization with flexibility, and predicts a shift in AI and chiplet adoption.
Its solutions range from stand-alone CPU cores to all-in-one designs (including NPUs) built around tensor, vector, and CPU combinations. One of Semidynamics’ key differentiators is its emphasis on memory bandwidth and customization. Features like the Gazzillion TLB (translation lookaside buffer) and configurable memory subsystems allow designers to adapt processors to specific workloads, particularly for AI and data-intensive applications.
In an interview with JPR’s David Harold, Semidynamics CEO Roger Espasa talks about the company’s RISC-V IP and what he envisions for RISC-V’s future.
To read the full article, click here
Related Semiconductor IP
- 64-bit Out-of-Order RISC-V Customisable IP Core
- 64-bit in-order RISC-V Customisable IP Core
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
Related News
- The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa
- Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
- Semidynamics: From RISC-V with AI to AI with RISC-V
- Semidynamics on major recruitment drive for RISC-V software engineers
Latest News
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP
- Lattice Semiconductor and Missing Link Electronics Become Partners to Accelerate FPGA Design Projects