High Bandwidth In-Order RISC-V IP Core

Key Features

• 64-bit Core
• Ready for the most demanding workloads, Avispado supports large memory capacities with its 64-bit native data path.
• With its complete MMU support, Avispado is also Linux-ready, including multiprocessing.
• Vector Ready (optional VPU 823 - RISC-V vector unit)
• Avispado supports the upcoming RISC-V Vector Specification 1.0 as well as Semidynamics Open Vector Interface, giving you freedom of choice between your own custom vector unit and using Semidynamics offerings.
• Vector Instructions densely encode lots of computations, thereby reducing energy per operation.
• Vector Gather instructions support sparse tensor weights efficiently, helping machine learning workloads.
• Multiprocessor Ready
• Avispado supports cache-coherent Multiprocessing environments. Its native CHI interface can be tailored down to ACE or AXI, depending on your needs.
• Be it 2, 4, or hundreds of cores, Avispado is ready for your next SOC.

Benefits

• Decodes 2 instructions/cycle
• In-order issue
• Gazzillion Misses™
• SV48
• Direct hardware support for unaligned accesses
• Customizable
• I$ from 8KB to 32KB
• D$ from 8KB to 32KB
• Branch Predictor
• Vector ready (optional VPU 823 -RISC-V vector unit)

Technical Specifications