High Bandwidth Out-of-Order RISC-V IP Core
Key Features
- 64-bit Core
- Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path.
- With its complete MMU support, Atrevido is also Linux-ready, including multiprocessing.
- Vector Ready (optional Vector Unit 823 - RISV V Vector unit)
- Atrevido supports RISC-V Vector Specification 1.0 as well as SemiDynamics Open Vector Interface, giving you freedom of choice between your own custom vector unit and using Semidynamics offerings.
- Vector Instructions densely encode lots of computations, thereby reducing energy per operation.
- Vector Gather instructions support sparse tensor weights efficiently, helping machine learning workloads.
- Multiprocessor Ready
- Atrevido supports cache-coherent Multiprocessing environments. Its native CHI interface can be tailored down to ACE or AXI, depending on your needs.
- Be it 2, 4, or hundreds of cores, Atrevido is ready for your next SOC.
- Optional full or partial Crypto extension to choose from.
Benefits
- Decodes 4 instructions/cycle
- Register Renaming
- Including V-regs
- Out-of-Order issue and completion
- Commit 4 instructions per cycle
- Gazzillion Misses™
- SV48 and SV57