Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies
San Jose, Calif., Nov. 17, 2009 - Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, today announced that Fujitsu Kyushu Network Technologies, a leader in innovative technologies for network and service management solutions, has adopted its SpyGlass®-CDC product. Fujitsu Kyushu Network Technologies will broadly deploy the tool to help reduce design risks associated with semiconductor IP integration.
Early Design Closure solutions from Atrenta allow design capture, verification, optimization and exploration early in the design flow at the register transfer language (RTL) stage, when it's faster and easier to correct problems and explore alternatives. This approach facilitates propagation of design efficiencies to detailed, back-end implementation with minimized schedule risk.
Atrenta's SpyGlass-CDC product analyzes system-on-chip (SoC) designs to ensure complex clock synchronization schemes such as FIFOs and handshakes are correct. Bugs in faulty clock domain synchronizations between IP blocks on a chip are hard to find with conventional design tools and represent a leading cause of chip re-spins and field reliability issues. "Atrenta's SpyGlass-CDC product allows us to ensure correct clock synchronization in our complex ASIC and FPGA designs," said Yuji Yoshitani, senior engineer at Fujitsu Kyushu Network Technologies System Logic Development Center. "We have deployed SpyGlass-CDC as a mandatory part of our ASIC and FPGA design flows to verify correct synchronization as early as possible and allow us to take corrective action if necessary."
"The use of third party semiconductor IP from multiple sources, with multiple clock domains, is a fact of life these days for complex SoCs," said Mike Gianfagna, vice president of marketing at Atrenta. "Our SpyGlass-CDC product is very effective at finding clock synchronization bugs that can easily become chip killers. We're delighted that Fujitsu Kyushu Network Technologies has chosen SpyGlass to assist with their leading edge designs."
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com.
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Qualitas Semiconductor Signs Licensing Agreement with Chinese SoC Company for DSI-2 Controller and MIPI PHY IP
- Brite Semiconductor Releases PCIe 4.0 PHY IP
- Leader And IntoPIX Boost IP Stream Monitoring With JPEG XS Integration
Latest News
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing
- Weebit Nano Q2 FY26 Quarterly Activities Report
- Arasan announces the immediate availability of the industries first xSPI NOR + eMMC NAND Combo PHY IP
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data