Momentum Builds on RISC-V European Adoption
EU funding model needs more industrial focus.
By Pablo Valerio, EETimes | June 9, 2025
Paris – As the RISC-V Europe Summit convened in Paris, the open standard instruction set architecture (ISA) continued its march towards mainstream adoption, sparking discussions among European experts about the continent’s role, its unique strengths, and persistent challenges.
In an exclusive interview for EETimes, Teresa Cervero of the Barcelona Supercomputing Center and Stefan Wallentowitz from Munich University of Applied Sciences, members of the RISC-V Summit Europe steering committee, offered their perspectives from the heart of European academia and research, areas instrumental in fostering the early growth of RISC-V.
To read the full article, click here
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Related News
- CEO interview: Globalfoundries' Tom Caulfield on the European project
- Hewlett Packard Enterprise and SiPearl Partner to Develop HPC Solutions with European Processors and Accelerate Europe's Adoption of Exascale Supercomputers
- The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa
- RISC-V Turns 15 With Fast Global Adoption
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation