32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue

600 Series Single Core Features

• RISC-V RV32 IMACFDBPKVZfh/Zcxlcz and RV64 IMACFDPBKVZfh/Zc ISA supported
• Dual Issue, in-order 6 stage Harvard Pipeline
• 64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
• Double, Single and Half-Precision floating point
• Configurable SIMD DSP Extension
• Full Vector Extension with 128-b VLEN
• Configurable ILM/DLM (Instruction Local Memory) with ECC
• Configurable ICachewith ECC
• Configurable DCache with ECC
• Configurable MMU supported (SV32/SV39/SV48)
• PMP and TEE supported to meet the system security requirement
• Full standard debug function with JTAG and cJTAG
• Full standard RISC-V toolchain with Linux\Windows IDE supported

600 series SMP Multi Core Features

• Dual-mode feature supported (Application Processor mode and Real-time Processor mode)
• Up to 16 SMP cores in one Cluster
• SoC Connectivity
• Configurable Cluster Memory Port(64/128/256/512-bit)
• Cluster Peripheral Ports support 32-bit AHB-Lite protocol
• Up to 16 IOCP (I/O Coherent Port) Ports supported
• Support Hardware Data Prefetching mechanism
• Cluster Cache
• Configurable Cluster Cache size
• Configurable Cacheline size（64Bytes）
• Configurable multi-cycle Tag RAM and Data RAM
• Support cacheline LOCK, FLUSH and INVAL operations
• 16-way associative
• Can be configured to Cluster Local Memory

• Real-time Feature
• RV32 IMACFDBPKVZfh/Zcxlcz, RV64 IMACFDPBKVZfh/Zc
• 6 Stage Pipeline Dual-issue
• I/D Cache
• Security(PMP, TEE)
• SP/DP FPU
• NICE Extension
• AXI system bus
• RISC-V Standard Debug
• JTAG & 2-wire JTAG
• Low Latency Interrupt
• Full Dev Kit & SDK