64-Bit RISC-V High Performance Processor
Overview
UX600 Series is also highly configurable for customers to add or remove hardware feature to optimize for their SoC.
Key Features
- RISC-V RV32 IMACFDPBKZfh/Zcxlcz?RV64 IMACFDPBKZfh/Zc ISA supported
- Single Issue, in-order 6 stage Harvard Pipeline
- 64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
- Double, Single and Half-Precision floating point
- ConfigurableSIMD DSP Extension
- Configurable Instruction and Data Memory
- Configurable ILM (Instruction Local Memory) with ECC
- Configurable DLM (Data Local Memory) with ECC
- ConfigurableMMU supported(SV32/SV39)
- PMP supported and TEE supported to meet the system security needs
- Full Standard Debug Function with JTAG and cJTAG Port
- Full Standard RISC-V Toolchain, and Linux\Windows IDE supported
Block Diagram
Technical Specifications
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