Path to 2nm May Not Be Worth It
Diminishing returns may evaporate at 5nm
Rick Merritt, EETimes
3/23/2018 01:01 AM EDT
SANTA CLARA, Calif. — Engineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure they will be able to squeeze commercial advantages from them even at 5nm.
The increasing complexity and cost of making ever smaller chips is leading to diminishing returns. Data rates are peaking at 3 GHz for mobile processors, and power and area gains will narrow at 7nm, said a Qualcomm engineer in a panel at a Synopsys user group event here.
Speed gains of 16 percent at 10nm may dry up at 7nm due to resistance in metal lines. Power savings will shrink from 30 percent at 10nm to 10-25 percent at 7nm, and area shrinks may decline from 37 percent at 10nm to 20-30 percent at 7nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.
For decades, the electronics industry followed a roadmap codified by Moore’s Law of doubling the number of transistors on a chip roughly every two years. The result was a fast pace of ever smaller, faster, cheaper products from PCs to smartphones.
To read the full article, click here
Related Semiconductor IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
Related News
- The IP double standard: Why is it OK to pay for innovation in a product, but not when innovation is the product?
- Like it or not, IP's here to stay
- Four reasons why MIPS new cores may make it relevant again
- Apple, HTC patent deal may not open Android door
Latest News
- Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash