Panel confronts multicore pros and cons
Richard Goering, EE Times
(03/23/2006 8:42 PM EST)
SANTA CLARA, Calif. — Panelists at the Multicore Expo here Wednesday (March 22) generally agreed that multitasking and multiprocessing have bright futures, although they identified some challenges as well. One of those challenges is the difficulty of programming next-generation multicore ICs.
Multithreading, said Michael Uhler, CTO of MIPS Technologies, provides an increase in performance without compromising power. He said the number of cores may be reduced as cores take on more capabilities, including multithreading. That's consistent with MIPS' position in February, when the company rolled out its MPS34K, a "virtual CPU" core that MIPS believes can forestall the need to move to multicore designs for some multimedia and network applications.
Heterogenous or asymmetric multiprocessing (AMP) multicore systems-on-chip (SoCs) are being built because they have lower bill of materials costs, Uhler said. "It wouldn't surprise me to see SMP [symmetric multiprocessing] on the host processor, with the system remaining AMP because of the BOM cost," he said.
(03/23/2006 8:42 PM EST)
SANTA CLARA, Calif. — Panelists at the Multicore Expo here Wednesday (March 22) generally agreed that multitasking and multiprocessing have bright futures, although they identified some challenges as well. One of those challenges is the difficulty of programming next-generation multicore ICs.
Multithreading, said Michael Uhler, CTO of MIPS Technologies, provides an increase in performance without compromising power. He said the number of cores may be reduced as cores take on more capabilities, including multithreading. That's consistent with MIPS' position in February, when the company rolled out its MPS34K, a "virtual CPU" core that MIPS believes can forestall the need to move to multicore designs for some multimedia and network applications.
Heterogenous or asymmetric multiprocessing (AMP) multicore systems-on-chip (SoCs) are being built because they have lower bill of materials costs, Uhler said. "It wouldn't surprise me to see SMP [symmetric multiprocessing] on the host processor, with the system remaining AMP because of the BOM cost," he said.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related News
- Letter to the editor: IP pros, cons (Jonah Probell)
- NXP CoolFlux BSP's 12-bit computation has pros and cons for low-power baseband
- Taiwan confronts SoC obstacles
- Panel debates value of mixed-signal design tools
Latest News
- TES offers CAN Flexible Data-Rate Controller IP Core for System-on-Chip (SoC) Designs
- Impinj and EM Microelectronic Announce Gen2X Licensing Agreement
- LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions
- Global Semiconductor Sales Increase 29.8% Year-to-Year in November
- BAE Systems Licenses Time Sensitive Networking (TSN) Ethernet IP Cores from CAST