Nuvation Introduces GEOS 2+2 IP Core
Lowest-Cost Ethernet-Over-SONET Solution for OC-48 Applications
SAN JOSE, CA -- (MARKET WIRE) -- 11/12/2003 -- Nuvation introduces the GEOS 2+2, a licensable FPGA IP Core that multiplexes and de-multiplexes two Gigabit Ethernet (GbE) data streams plus two Fast Ethernet (FE) channels into a single OC-48 channel.
The IP core is designed to interface between a 4-port Gigabit Ethernet MAC such as the Intel® IXF1104 and a 2.488Gbit/s SONET/SDH Framer Device such as the PMC® PM5381 over a POS-PHY Level 3 interface. The GEOS 2+2 supports up to 20% more bandwidth at 30% lower cost than competitive ASIC solutions.
Additional features of the GEOS 2+2 include side band full duplex pause control flow, configurable destination port addresses, and GbE and FE traffic statistics per port. The GEOS 2+2 is designed for integration with Altera POS-PHY Level 3 (PL3) cores and is optimized for the Altera® Cyclone EP1C20 device architecture.
Altera Corporation has verified the GEOS 2+2 and given it their AMPP(SM) and Atlantic-compliant approvals. The GEOS 2+2 is the newest member in a family of GEOS cores from Nuvation. Nuvation GEOS cores, such as the GEOS-10, can multiplex up to 10 channels of GbE to OC-192 and have been licensed and hardware validated.
"The Altera Cyclone is the perfect FPGA platform technology for the GEOS. It's extremely low cost, which is a tremendous advantage to our customers over competitive ASSP solutions. This is an excellent example of the FPGAs taking market share from ASIC vendors," said Michael Worry, CEO of Nuvation. "In addition to the GEOS-10, GEOS-8, and GEOS-2, the GEOS 2+2 will provide communications OEMs with high-reliability, high-availability solutions to reduce time-to-market and risk."
Gigabit Ethernet (GbE) is becoming the preferred communications protocol for LAN backbones, Video-On-Demand, Network Storage, and other high-speed networking requirements. Long haul and metro area network architectures were designed to carry voice data on a SONET ring topology. The GEOS 2+2 bridges these protocols and topologies to enable multi-channel GbE and Fast Ethernet traffic over SONET at up to 2.488 Gigabits per second, or OC-48 speeds. The GEOS 2+2 is currently optimized for the Altera® Cyclone device architecture and interfaces with Altera POS-PHY Level 3 cores, licensable from Altera Corporation. The GEOS 2+2 is available now. Source code licenses are also available. For more information, please email ipcores@nuvation.com.
About Nuvation
Nuvation is a leading Electronics Design Services (EDS) firm, providing FPGA, printed circuit board, and firmware design services as well as Signal Integrity Analysis consulting and licensable IP Cores. Founded in 1997 and is based in San Jose, California, Nuvation support clients globally in markets such as Consumer Electronics, Defense/Aerospace/Homeland Security, Medical Imaging, Semiconductor, and Communications. More information is available at www.nuvation.com
NUVATION is a registered trademark of Nuvation Research Corporation. All other company and product names may be trademarks of the company with which they are associated.
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
Related News
- DTS Audio Technologies for Blu-ray Disc and HD DVD to be Added to Tensilica's HiFi 2 Audio Engine
- Tensilica Adds Dolby Digital Consumer Encoder and Dolby Digital Compatible Output 5.1-Channel Encoders to Xtensa HiFi 2 Audio Engine Codec Library
- ASIC Architect Announces the Availability of PCI Express Gen 2 Controller Cores
- Lattice Announces ispLEVER 7.0 Service Pack 2 FPGA Design Tool Suite
Latest News
- EU DARE Project Is Scrambling to Replace Codasip
- Sofics and Alcyon Photonics Partner to Support Next-Generation Photonic Systems
- QuickLogic Appoints Quantum Leap Solutions as Authorized Sales Representative
- Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud