Nuclei Announces Strategic Global Expansion to Accelerate RISC-V Adoption in 2026
Shanghai, China — February 3, 2026 — Nuclei, a leading provider of high-performance semiconductor IP processing solutions, today announced a major strategic expansion of its global operations. To kick off the 2026 fiscal year, the company is establishing a stronger local presence across the US, EU (Europe), and the LEMEA (Latin America, Europe, Middle East, and Africa) regions.
This expansion is designed to bring Nuclei’s deep RISC-V expertise directly to regional markets, ensuring that innovators have seamless, local access to best-in-class processor IPs and complete subsystems. Recognizing that software maturity is the catalyst for hardware success, Nuclei is doubling down on its commitment to providing a "ready-tocode" experience.
By establishing a stronger local presence, Nuclei will better enable developers to leverage its comprehensive processing IP offerings, designed to eliminate the complexities of RISCV integration. Altogether, Nuclei aims to drastically reduce time-to-market for nextgeneration designs in sectors ranging from IoT and Consumer to Industrial and Automotive, including high-growth AI-enhanced applications.
Empowering Innovation Through Comprehensive Support
As the demand for open-standard architectures grows, the need for robust and scalable processing solutions has never been higher. To fuel customer demands, Nuclei provides:
- Seamless Integration: Providing comprehensive RISC-V processors to subsystems that simplify the design cycle for SoC (System-on-Chip) architects.
- Extensive Software Ecosystem: Full support with open-sourced and optimised solutions for software development, allowing engineers to focus on application-level innovation rather than low-level driver development.
- Scalable Solutions: Delivering an extensive portfolio of processor IPs designed to grow alongside the evolving needs of the semiconductor industry.
"Our goal for 2026 and forward is simple: to remove any barrier to RISC-V adoption," said Bob Hu, Founder of Nuclei. "By strengthening our local presence in the US, EU, and LEMEA, we aren't just selling processor IP solutions; we are becoming an embedded partner in our clients' innovation journeys. We want to ensure that every designer, regardless of their location, gets the speed, reliability, and openness they need to innovate without boundaries.
Explore RISC-V IP:
- 64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
- 32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
- 32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
Looking Ahead
This expansion marks the first of several major updates planned for the new year. Nuclei remains committed to the RISC-V ecosystem and will continue to roll out new product milestones and partnership announcements throughout 2026.
For more information about Nuclei and its RISC-V solutions, please visit www.nucleisys.com
About Nuclei System Technology
Nuclei is the industrial-grade standard for the RISC-V revolution. Founded in 2018 to bridge the gap between open-source flexibility and Tier-1 reliability, Nuclei provides a silicon-proven portfolio of RISC-V CPU IP ranging from ultra-low-power 32-bit nodes to high-performance 64-bit multi-core engines with AI extensions. With nearly 1 billion units shipped and over 300 global customers, Nuclei delivers ARM-grade reliability through a strict "Triple-A" framework: Architectural Integrity, Application Readiness, and Accountability. As the first vendor to achieve ISO 26262 ASIL-D certification for RISC-V, Nuclei empowers silicon sovereignty for the automotive, security, consumer and industrial markets worldwide.
Learn more at: www.nucleisys.com
Related Semiconductor IP
- 64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
- 32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
- 32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
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