New Platform-Based Design Capabilities Expand CoWare's Proven Tools And Methods to Speed New and Derivative Products to Market
New Platform-Based Design Capabilities Expand CoWare's Proven Tools And Methods to Speed New and Derivative Products to Market
SANTA CLARA, Calif., Aug. 21 -- CoWare(TM), Inc., the leading provider of system-level design tools, has added new platform-based design capabilities to its CoWare N2C(TM) design system. The new capabilities include improved creation of virtual platform models, enhanced Interface Synthesis(TM) for multiple processor platforms, and easier integration of the system software with the platform.
``For the first time, platform-based design can be done at the system level, incorporating both hardware and software,'' stated CoWare President and CEO Guido Arnout. ``CoWare's customers are leading the way in establishing platform-based design as the prevalent methodology for creation and use of core-based architectures that can be rapidly extended and customized for a range of applications. This allows some degree of stability to be brought to the System-on-a-Chip (SoC) design process, while retaining the flexibility necessary to meet demand for new and derivative products.''
Philippe Geyres, Corporate Vice President and General Manager of ST's Consumer and Microcontroller Groups, said, ``ST is extensively using CoWare tools for the development and verification of its Product Platforms for Digital Consumer. It is also using them to enable its customers to start their system development before the availability of final silicon products. CoWare helps ST cut the time to volume of its system-on-a-chip for Digital Consumer, a segment where ST is the established leader.''
The Virtual Platform -- Taking Virtual Prototypes to the Next Level
CoWare N2C virtual prototypes give software designers an early accurate model of the hardware to develop and test their software, so they don't have to wait for the hardware prototype to start software development. The availability of a hardware prototype is problematic at best in a SoC design flow.
Platform-based design takes the concept of a virtual prototype a step further. Now, using CoWare N2C, designers can create a system-level platform that can be rapidly customized for a range of applications. First, the platform creator builds a base system around core intellectual property (IP) including CPUs, DSPs, memories, buses and peripherals. Usually, the base platform is developed from knowledge of the application's requirements or architectural specifications from the system-house customer, at a very early stage before the functional system specification is complete. Performance of the platform can be evaluated using CoWare N2C's advanced analysis capabilities.
Then this base platform can be delivered to a system designer, who adds system IP to the platform by developing software and/or by adding extra hardware blocks to the system. As more features are added, core IP blocks or application-specific peripherals can easily be swapped in and out using CoWare N2C's Interface Synthesis(TM) capabilities to generate all the necessary communication and glue logic. Synthesized components can include address decoding, interrupt priority encoding, arbitration units, memory mapped registers, program and data memory and controllers, interrupt service routines, boot code, methods to access memory mapped registers, etc. The result is a ``plug and play'' method enabling the rapid creation of many derivatives.
Interface Synthesis for Multi-Processor Platforms
Often, designers want to combine multiple CPUs and DSPs in the same design. CoWare N2C has long allowed designers to model and simulate these multi-processor SoC designs. However, only one processor was available as a target for partitioning the system specification and hardware-software Interface Synthesis. Now, CoWare N2C will allow system functionality to be partitioned between hardware and software for multiple processors. Interface Synthesis will create the hardware-software communication and glue logic for each processor sub-system in turn.
Integration of System Software with the Platform
In a platform-based design flow, the hardware-software partition may be largely pre-defined and the remaining design task is to integrate the system software onto the platform as easily as possible. CoWare's Interface Synthesis capabilities automatically generate the software interfaces to the hardware. Now CoWare has added a capability to automatically create a clear unambiguous Application Programming Interface (API) to the platform. This API consists of software files detailing the platform's memory map and software drivers, and automated assistance to build the software image and compile it onto the platform.
Pricing and Availability
These new capabilities are currently in beta testing and will be phased into CoWare N2C, for shipment by the end of the year, at no extra charge.
About CoWare
CoWare, Inc., provides tools and methodologies that help engineering teams cut their system-on-a-chip design times in half. CoWare N2C(TM) provides an efficient means to capture, analyze, and implement a system specification, with parallel development by hardware and software teams. In addition, CoWare N2C greatly enhances IP re-use and selection, further reducing design time. The CoWare N2C software is employed by major systems and semiconductor companies including Alcatel, Fujitsu, Mitsubishi, Motorola, Nokia, Sony and STMicroelectronics. CoWare is headquartered in Santa Clara, Calif. USA and employs over 100 people. For more information, visit www.CoWare.com.
CoWare, CoWare N2C, and Interface Synthesis are trademarks of CoWare, Inc.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related News
- Efabless Unveils New Custom Chip Platform Designed for Edge ML Products
- Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration
- Synopsys' DesignWare STAR Memory System's New Test and Repair Capabilities Speed Embedded Memory Repair Time by 10x
- Spectral releases Silicon proven High Speed Low Power SRAM compilers in the 40/45nm CMOS/RFSOI process nodes targeted for a wide range of IOT & 5G Applications
Latest News
- Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms