MegaChips Adopts Cadence RTL-to-Signoff Solution, Cuts Tapeout Schedule in Half

Cadence technology suite provides 9 percent frequency increase and 8 percent power reduction on their ARM Cortex-A9 design

SAN JOSE, Calif., 30 Jun 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that MegaChips has cut its tapeout schedule in half by using the Cadence® digital RTL-to-Signoff solution. In addition to getting their products to market faster, MegaChips leveraged Cadence Encounter® RTL Compiler and Cadence Encounter Digital Implementation (EDI) System, and achieved a 9 percent frequency increase and an 8 percent power reduction on their dual-core ARM® Cortex®-A9 design.

MegaChips also utilized the Cadence digital RTL-to-Signoff solution to address implementation challenges in hierarchical design/partitioning, congestion handling and better clock tree synthesis (CTS) structures. Encounter RTL Compiler’s unique physically aware datapath optimization technology was able to reduce the area of critical blocks in the MegaChips design, while enabling faster timing closure through access of physical data earlier on in the design flow. The EDI System’s multi-threaded GigaOpt physical optimization and CCOpt concurrent clock-data-path optimization with useful skew resulted in faster turnaround time with improved performance, and leakage and dynamic power.

“We adopted Cadence RTL-to-Signoff solution to address two main challenges on our ARM-based designs: power/performance and schedule,” said Mr. Gen Sasaki, director and office general manager of the AS Business Headquarters of MegaChips. “We leveraged advanced physically aware synthesis technology from RTL Compiler to better structure and map the logic into an optimized layout-friendly netlist. The EDI System’s GigaOpt and CCOpt technologies helped further realize better design performance and lower power, while improving our design team productivity.”

“Collaborating closely with MegaChips enables us to meet and exceed their design requirements and time-to-market goals,” said Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. “The Cadence RTL-to-Signoff solution brings significant power/performance and schedule improvements to MegaChips’ multi-core and high-performance designs.”

To learn more, please visit www.cadence.com/products/di/edi_system/pages/default.aspx.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.