Dolphin Integration launches the kit of cells to build islets of the second generation
Grenoble, France -- February 8, 2013 -- Dolphin Integration is releasing SESAME CLICK, a kit of cells enabling the construction and integration of islets. Its low power cells optimized for TSMC 65 nm and 55 nm processes is enriched with a patented Transition Ramp Cell for an easy and safe construction of low energy circuits.
SESAME CLICK minimizes power consumption through:
- Support of logic blocks with multiple voltages, through level shifters.
- Support of power gating with or without retention of data, through always-on cells, retention spinner cells, isolation cells, filler cells, corner cells and of course power switches.
The 65/55 nm CLICK, coupled with the intrinsic density advantages of 6-Track standard cell library, SESAME uHD-BTF, enables SoC designers to reach whatever leakage reduction they aim at!
SESAME CLICK leaves far behind the first generation of cells for power management.
For reaching top performances, Dolphin’s CLICK features
- « Retention spinner cells » with pulsed latches replacing retention flip-flops with balloon latches for up to a 4-times gain in density!
- Scripts for automatic computation of the optimal number of switches required for islet construction
- Low voltage retention capability down to 0.77 V at 65/55 nm.
SESAME CLICK is not only a power and cost effective solution, but also a solution guaranteeing a straightforward integration of islets, to solve the key issues of in-rush current, of islet integration and of switch placement.
Advanced features for a successful integration of power and voltage islets
- The patent-pending Transition Ramp Cell (TRC) handles an automated limitation of the inrush current caused by mode transitions
- The ring style for switch placement enables easy integration of hard macros
- CLICK is provided together with a script ensuring the automated insertion of the ring and the sizing of the switches
- The associated transfer of know-how in modeling and simulation helps guiding the user to size any power regulator with its islet and conversely.
For more information, feel free to download the Presentation Sheet.
For performing fast your own benchmark of this silicon IP on your design, just click here and request an access to the evaluation kit.
Our Integration and Application Engineers provide support to define the most suited combination of silicon IPs and the best SoC architecture for your project.
Please contact sesame@dolphin.fr for more information.
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. Such diverse experience in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Frontgrade Gaisler is proud to be a part of the ePERFECT project
- DNP Invests in Rapidus to Support the Establishment of Mass Production for Next-Generation Semiconductors
- MIPS and INOVA Collaborate to put Physical AI into the palm of Robotic hands with new Reference Platform
Latest News
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs
- Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions