IPrium releases 100 Gbps Polar Encoder and Decoder
FOGGIA, Italy -- December 22, 2022 - FPGA intellectual property (IP) provider IPrium LLC (www.iprium.com) has today announced that it has expanded its family of multigigabit FEC Encoder and Decoder IP products with a new 100 Gbit/s Polar FEC.
The 100 Gbps Polar Codec IP Core supports code block length (N) of 1024 bits, payload length (K) from 100 to 1000 bits with fully-parallel and unrolled architecture. The IP Core is customizable to any standard, including 3GPP 5G.
Pricing and Availability
The 100 Gbps Polar Encoder and Decoder IP Core is available immediately in synthesizable Verilog or optimized netlist format, along with synthesis scripts, simulation test bench with expected results, and user manual. For further information, a product evaluation or pricing, please visit the IP Core page:
About IPrium LLC
IPrium Modem IP Cores allow designers of communication equipment to rapidly develop and verify their systems in a highly cost-effective manner. IPrium offers FPGA IP Cores for high-quality wireless and wireline modems. Visit IPrium at www.iprium.com.
Related Semiconductor IP
- 5G IoT DSP
- 5G RAN DSP
- Polar Encoder / Decoder for 3GPP 5G NR
- LDPC Encoder / Decoder for 3GPP 5G NR
- 5G Polar Intel® FPGA IP
Related News
- Creonic Shows 100 Gbps Polar Decoder in International SENDATE-TANDEM Research Project
- IPrium releases CCSDS TC Telecommand LDPC Encoder and Decoder
- IPrium releases IEEE 802.11n/ac/ax LDPC Encoder and Decoder
- IPrium releases CCSDS TM Telemetry AR4JA LDPC Encoder and Decoder
Latest News
- Cyient Semiconductors Enters Strategic Channel Partnership with GlobalFoundries
- Aion Silicon Successfully Completes ISO 9001 and ISO/IEC 27001 Surveillance Audit, Strengthening Commitment to Quality and Security
- Baya Systems Awarded Globally Recognized ISO 9001:2015 Certification for Quality Management by TÜV Rheinland
- Si2 Announces Creation of the Si2 LLM Benchmarking Coalition
- Qualitas Semiconductor Signs Licensing Agreement with Chinese SoC Company for DSI-2 Controller and MIPI PHY IP