Intel sees quad-patterned path to 10 nm chips
Rick Merritt, EETimes
9/12/2012 11:00 PM EDT
The 10 nm process would debut in 2015 or later. It would require quadruple patterning for some mask layers but “it’s still economical,” said Mark Bohr, director of Intel’s technology and manufacturing group, speaking to EE Times after a talk at the Intel Developer Forum here.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- TSMC Says Immersion Lithography Nearly Production Ready
- UMC Adopts Synopsys IC Validator for Pattern Matching-Based Lithography Hot-Spot Verification at 28 nm
- Intel Reports Tepid Progress on 10 nm
- Synopsys Delivers Certified EDA Flows and High-Quality IP for Intel 16 Process
Latest News
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs