Intel's 22-nm tri-gate SoC, how low can you leak?
Sylvie Barak, EETimes
12/10/2012 4:30 PM EST
SAN FRANCISCO -- Intel will describe its 22-nm tri-gate (FinFET) SoC technology for mobile applications Monday (Dec. 10) at the International Electron Devices Meeting (IEDM) here.
The chip maker introduced a CPU version of its 22-nm offering in June, but Intel senior fellow Mark Bohr said in an interview that the recipe has been tweaked in order to scale down to a more mobile, ultra-low leakage version.
To read the full article, click here
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
- 0.9V/2.5V I/O Library in TSMC 55nm
- 1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
Related News
- Intel tips 22-nm tri-gate, but mobile is MIA
- Tabula Confirms Move to Intel's 22nm Process Featuring 3-D Tri-Gate Transistors
- Intel Foundry and Arm Announce Multigeneration Collaboration on Leading-Edge SoC Design
- Arasan announces the immediate availability of its 2nd Generation MIPI D-PHY for GlobalFoundries 22nm SoC Designs
Latest News
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications
- GUC Announces Tape-Out of the World's First HBM4 IP on TSMC N3P
- lowRISC and SCI Semiconductor Release Sunburst Chip Repository for Secure Microcontroller Development
- BrainChip Partners with RTX’s Raytheon for AFRL Radar Contract