Hitachi, Triscend ink deal to co-develop configurable RISC processors
Hitachi, Triscend ink deal to co-develop configurable RISC processors
By Semiconductor Business News
January 23, 2001 (9:58 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010122S0053
TOKYO -- Japan's Hitachi Ltd. has announced plans to enter the configurable RISC chip market as part a product development alliance with Triscend Corp. Under the terms, Hitachi will integrate Triscend's configurable chip technology across its SuperH line of 32-bit RISC processors. In addition, Hitachi will gain access to Triscend's configurable FastChip software, intellectual-property (IP) cores, and third-party EDA tools. The configurable SuperH-based devices, to complement Hitachi's existing SuperH chips, are geared for advanced communications and other applications, according to officials from Hitachi. "Triscend provides us with leading edge [configurable system-on-a-chip] technology that will enhance the leadership position of the SuperH among RISC processors worldwide," said Kunio Hasegawa, executive vice president of semiconductor and integrated circuits of Tokyo-based Hitachi. "Combining our SuperH architecture with Triscend's p latform will result in shorter development time and lower development costs for end systems," he said. Hitachi's configurable SuperH-based devices will also expand Triscend's existing 8051- and ARM7-based platforms, giving designers a richer choice of processors for off-the-shelf system-on-a-chip solutions, said Stanley Yang, president and chief executive of Mountain View, Calif.-based Triscend. Triscend's platform consists of several parts, including the CSI (Configurable System Interconnect) bus, the CSL (Configurable System Logic) embedded programmable logic matrix, and the CSI socket. The CSI bus is a processor-independent, scalable technology, which is designed for various applications. Hitachi's first configurable SuperH-based devices will be available in 2002.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- SuperH names executives at RISC chip venture between Hitachi and STMicro
- STMicro, Hitachi plan new company to develop RISC cores
- Hitachi, STMicro to develop 64-bit RISC for consumer apps
- Jasper, AMD Ink Long-Term Formal Verification Deal
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack