GUC Tapes Out Industry-Leading UCIe Face-Up IP for TSMC SoIC-X

Hsinchu, Taiwan – July 15, 2025 – Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful tape-out of the industry-leading Universal Chiplet Interconnect Express™ (UCIe™) PHY Face-Up IP on TSMC’s N5 process for integration with the TSMC SoIC®-X technology. Targeted for AI, HPC, xPU, and networking applications, the IP achieves a breakthrough 36Gbps performance with Adaptive Voltage Scaling (AVS), delivering 2× better power efficiency at the required data rate. This solution offers an industry-leading bandwidth density of 1.5TB/s per mm of die edge. The chip was assembled using TSMC’s advanced SoIC-X and CoWoS® (Chip-on-Wafer-on-Substrate) packaging technologies.

Earlier this year, GUC demonstrated UCIe-32G silicon on the TSMC N3P process at the TSMC 2025 North America Technology Symposium. In 2024, GUC also taped-out its UCIe LP (Low Power) solution featuring AVS on the TSMC N5 process, aimed at meeting the growing bandwidth demands of multi-die integration in AI, HPC, and networking applications. Leveraging extensive experience in 3D interface IP and SoIC design, GUC developed Face-Up version of UCIe LP IP, enabling robust die-to-die interconnect for the bottom die of SoIC-X configurations. Looking ahead, GUC is actively developing UCIe 64G IP, with plans to tape out by the end of 2025, addressing the ever-growing need for higher bandwidth in next-generation chiplet-based systems.

To reduce PHY power consumption, all GUC UCIe LP IPs incorporate Adaptive Voltage Scaling (AVS), optimizing supply voltage and driving strength to improve power efficiency by up to 2x. A training algorithm dynamically selects minimal voltage and drive strength to meet eye margin criteria, ensuring reliable operation under varying voltage and temperature conditions. Additionally, the IP integrates proteanTecs’ I/O signal quality monitors, allowing real-time performance monitoring without the need for re-training or data transfer interruption.

For easy integration, GUC has developed bridges for AXI, CXS, and CHI buses utilizing the UCIe Streaming Protocol. These bridges are optimized for high traffic density, low latency, and low power, with efficient end-to-end flow control, facilitating a seamless transition from single-chip NoC architectures to chiplet-based systems. They support Dynamic Voltage and Frequency Scaling (DVFS), enabling on-the-fly changes in digital supply voltage and bus frequency while maintaining uninterrupted data flow.

“With industry-leading UCIe solutions now available on the TSMC N5 and N3P technologies, we are excited to introduce the brand new UCIe Face-Up IP for SoIC-X, supporting 36Gbps with twice the power efficiency,” said Aditya Raina, CMO of GUC. “We’ve built a complete, silicon-proven 2.5D/3D chiplet IP portfolio across TSMC’s 7nm, 5nm, and 3nm process technologies. Combined with our expertise in design, package integration, electrical and thermal simulation, DFT, and production testing, we deliver a comprehensive solution that accelerates development cycles and product ramp-up for AI, HPC, xPU, and networking customers.”

“Our mission is to provide the fastest and lowest-power 2.5D/3D chiplet interface IPs, enabling a smooth transition from monolithic SoCs to modular chiplet architectures,” added Igor Elkanovich, CTO of GUC. “The convergence of 2.5D and 3D packaging, leveraging HBM3/4, UCIe, and GLink-3D interfaces, paves the way for highly modular processors that exceed traditional reticle limits.”

GUC UCIe LP Face-up IP Highlights

• Support SoIC-X bottom die
• Signed off at 36Gbps per lane
• Bandwidth density: 1.5TB/s per mm
• Adaptive Voltage Scaling (AVS) for 2x better PHY power efficiency
• AXI, CXS and CHI bus bridges
• Dynamic Voltage and Frequency Scaling (DVFS) for user parallel bus
• Per-lane, in-mission mode I/O signal quality monitoring by proteanTecs

🔍 Learn more about our innovative UCIe IP portfolio on our website 👉 UCIe IP portfolio: GUC IP

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