Analysts fret over FPGA lead times
EETimes
10/20/2010 7:18 PM EDT
SAN FRANCISCO—Lead times for parts at the two firms that dominant the programmable logic market are shortening after being exaggerated by high demand for months. Analysts see the trend as a sign of slowing demand, though they appear divided on how severe the impact might be.
In reporting their quarterly results this week, Xilinx Inc. and Altera Corp.—which together account for some 85 percent of the programmable logic market—both reported improvement in lead times. Xilinx said average lead times were reduced during the quarter that closed Oct. 2 from 12 weeks to nine weeks, and that the firm expects average lead times to return to their historical normal of about four weeks by the end of the year.
To read the full article, click here
Related Semiconductor IP
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
Related News
- TSMC, UMC, start pushing out lead times
- SoC designs drive quest for short test times <!-- verification -->
- Motorola announces Design Documentation standard; provides a key to reduced cycle times and increased standardization
- MoSys Ranked First In Net Margin According To Semiconductor Times
Latest News
- CAST Introduces MAC-SEC-MG IP Core for Secure 10G+ Ethernet SoC Designs
- Crypto Quantique and Attopsemi Unite PUF and I-fuse® OTP technology to Deliver Zero-Overhead Device Enrollment on FinFET Technology
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory