Faraday Offers 0.13um miniIO with around 40% Area-Saving and Robust ESD Performance
Hsinchu, Taiwan and Sunnyvale, California -- Mar. 18, 2009 -- Faraday Technology Corporation (TAIEX: 3035) today announced the availability of its innovative IO offering at 0.13um, miniIO™. Compared with general IO pads, the advantage of Faraday's miniIO™ is its area reduction, up to 40% for a pad-limit design with 200 pins, and still keeping the same programming IO functionality, while achieving robust ESD performance. Targeting fabless design houses, Faraday's miniIO™ has been silicon proven via complete function verifications.
Faraday's miniIO not only contributes to a large scale of chip area saving, but also fits the most aggressive pad pitch rules from assembly houses (25um cell width in stagger miniIO), making it a perfect match to the pad-limit designs, especially for sophisticated and complex SoC designs. Furthermore, the miniIO™'s low input/output capacitance can help reduce IO's switching power, lowering overall power-consumption and achieving higher speed.
"Faraday has been committed to offering a complete series of mini IO libraries since 0.18um," said Eliot Chen, Associate Vice President of RD at Faraday, "and has been recognized to be greatly helpful to customers' chip area reduction. Inheriting our technology and market successes for years, we are confident that our newly-launched and under-developing miniIO™ will continuously assist customers to design their competitive and differentiated products," he added.
"Cohering with the success at 0.18um, the newly-launched and highly-evaluated miniIO™ at 0.13um relieves customers from the problems normally associated with pad-limit designs and ESD issues, further enhancing their product's reliability and overall performance." said Steve Wang, Chief Strategy Officer at Faraday. "Currently, Faraday has been catalyzed into a leading provider of miniIO™ contributed by the high competitiveness of 0.18um and 0.13 miniIO™ solutions and the fruitful market achievement, which has also brought lots of inquires for our under-developing 90nm, 65nm and 55nm miniIO™ serials.," he added.
Availability
Faraday's miniIO™ at 0.13um is now available, and can support BOAC. The miniIO™ at 90nm will be available in April; at 65nm/55nm will be ready in June.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com.
Faraday's miniIO not only contributes to a large scale of chip area saving, but also fits the most aggressive pad pitch rules from assembly houses (25um cell width in stagger miniIO), making it a perfect match to the pad-limit designs, especially for sophisticated and complex SoC designs. Furthermore, the miniIO™'s low input/output capacitance can help reduce IO's switching power, lowering overall power-consumption and achieving higher speed.
"Faraday has been committed to offering a complete series of mini IO libraries since 0.18um," said Eliot Chen, Associate Vice President of RD at Faraday, "and has been recognized to be greatly helpful to customers' chip area reduction. Inheriting our technology and market successes for years, we are confident that our newly-launched and under-developing miniIO™ will continuously assist customers to design their competitive and differentiated products," he added.
"Cohering with the success at 0.18um, the newly-launched and highly-evaluated miniIO™ at 0.13um relieves customers from the problems normally associated with pad-limit designs and ESD issues, further enhancing their product's reliability and overall performance." said Steve Wang, Chief Strategy Officer at Faraday. "Currently, Faraday has been catalyzed into a leading provider of miniIO™ contributed by the high competitiveness of 0.18um and 0.13 miniIO™ solutions and the fruitful market achievement, which has also brought lots of inquires for our under-developing 90nm, 65nm and 55nm miniIO™ serials.," he added.
Availability
Faraday's miniIO™ at 0.13um is now available, and can support BOAC. The miniIO™ at 90nm will be available in April; at 65nm/55nm will be ready in June.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
- CAN-FD Controller
Related News
- Arasan Chip Systems Introduces First eMMC v5.0 I/O PADs & PHY IP using TSMC 28nmHPM Process
- Princeton Technology Group Partners with Altera to Provide High-Speed I/O Evaluation Board
- TriCN'S SPI-4.2 I/O Interface Technology Supports NPFSI, SFI and SPI Standards
- LEDA Systems® Introduces DBA (Direct Bump Access) FlipChip Ready I/O Library For 0.13 and 0.10-micron advanced CMOS processes
Latest News
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP