Dolphin Integration and IBM accelerate mixed signal SoC verification through "dynamic Specification Rule Checking"
GRENOBLE, France - September the 24th, 2002 - Thanks to its competencies both as a Virtual Component provider and as an EDA provider, Dolphin Integration provides its customers with innovative solutions to facilitate the integration and verification of Virtual Components within a System-on-Chip.
IBM's FoCs which is a converter from the Sugar assertion language to the Verilog and Vhdl design languages, combined with Dolphin's SMASH, a single engine mixed signal multi level simulator, enables designers to develop checkers in SUGAR and integrate them both in Verilog and VHDL simulations.
It thereby provides assertion checks beyond the mere testbench and enabling verification throughout SoC integration. Furthermore, the non exhaustiveness of behavioral models is no longer a problem as rules which are too difficult to verify in the models can now be provided as add-on checkers, for instance to verify that synchronisation signals meet the specifications.
Thus, SUGAR checkers extend the SMASH Platinum simulator dynamic Electrical Rules Checking to dynamic Specification Rule Checking (dSRC(TM)), paving the way for future extensions to analog & mixed signal verification.
More information on :
http://www.dolphin-integration.com/medal/smash/smash_flash.html
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Siemens' state-of-the-art Symphony Pro platform expands mixed signal IC verification capabilities
- Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification
- TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite
- IBM Announces Industry's Densest, Fastest On-Chip Dynamic Memory in 32-Nanometer, Silicon-on-Insulator Technology
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack