Distributed In-Chip Thermal Sensors Improve Multicore CPU Monitoring
By Nitin Dahad, EETimes (June 15, 2020)
With silicon geometries scaling to 5nm, thermal activity escalates and monitoring becomes critical to maintaining accuracy and reliability. To address this, Moortec, a provider of in-chip monitoring, telemetry and analytics technology, has introduced a distributed thermal sensor (DTS) on TSMC’s N5 process, which it claims is significantly smaller and more accurate compared to current in-chip thermal sensor solutions.
In order to meet performance requirements in systems-on-chips (SoCs) employing FinFET technology with higher gate densities (and hence power densities), designers are facing challenges in providing reliable, power efficient and speed optimized chip designs. Thermal activity can be unpredictable and if not monitored carefully can cause over-heating and excessive power consumption which in turn impacts device longevity. The ability to make precise thermal measurements beside or within CPU cores, high speed interfaces or highly active circuitry has become a mandatory requirement for devices used within a range of application areas.
The new DTS sensing fabric enables distributed, real-time thermal analysis, enabling up to 16 remote probe points in a silicon area that Moortec said is seven times smaller than some standard in-chip thermal sensors. At a recent press briefing, Stephen Crosher, CEO of Moortec, said, “The DTS is smaller in size and integrates within the chip. It can run off the core supply to do the sensing so can sense deeper within the chip — this is important for larger die sizes.”
To read the full article, click here
Related News
- Moortec Launches New In-Chip Technology for Highly Distributed, Real-Time Thermal Analysis on TSMC N5 Process
- Arteris Redefines Heterogeneous Multicore Cache Coherency with Configurable, Distributed Semiconductor Architecture
- Socionext Develops New Large Scale, High Efficiency Distributed Processing Server, Fully Utilizing Multi-Core Processors
- Moortec to exhibit their embedded In-Chip Monitoring Subsystem IP at the 2017 TSMC OIP Ecosystem Forum in Santa Clara
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing