DCT boost ARC risc core with Java
DCT boost ARC risc core with Java
By Peter Clarke, EE Times UK
October 1, 2001 (7:56 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010917S0023
UK start-up Digital Communication Technologies has designed a Java byte code processor based on the ARCtangent-A4 32bit risc core. The company claims the processor achieves better Java performance than ARM Holdings' Jazelle technology but still at the same clock frequency. The core, known as Bigfoot, complements DCT's established offering, a Java and C-language processor based on a stack architecture, known as Lightfoot. Lightfoot has been available since mid-1999 as intellectual property (IP) suitable for downloading on to an FPGA. DCT executives now expect to have a Bigfoot-based microcontroller in foundry silicon by December and a Lightfoot microcontroller in silicon in January 2002. But DCT is not yet a license-holder for the ARCtangent-A4, an architecture developed by ARC International. DCT created Bigfoot for Fujitsu Microelectronics Europe under Fujitsu's ARC licence. Tony Webster, DCT chief executive, said: "We're in di scussion with ARC on licensing. We've added several thousand gates to the ARC core, thereby Java-enabling it." DCT has retained the IP around its Java extension to ARC and expects to sell Java microcontrollers for embedded applications based on both Bigfoot and Lightfoot cores. Peter Clarke is European correspondent for US sister newspaper EETimes.
Related Semiconductor IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
Related News
- Synopsys' New Superscalar ARC HS Processors Boost RISC and DSP Performance for High-End Embedded Applications
- DCT boosts prospects for embedded Java
- DCT Announces Highest-Performance Java Solution for Wireless Devices - Bigfoot Java Acceleration Technology Surpasses 10 Caffeine Mark Barrier
- ARC: from 3D Game Chips to Licensable RISC Processor
Latest News
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware