Digital Blocks Announces the DB-I2C Controller IP Core with the availability of Master-Slave, Master, and Slave Versions for the AMBA 2.0 APB Interconnect
Specifically targeted for Embedded Processor designs with AMBA 2.0 APB Bus requirements, the DB-I2C offers a variety of performance levels versus VLSI footprint tradeoff options.
GLEN ROCK, New Jersey, December 20, 2007 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for embedded processor and video system designers, today announces the DB-I2C Controller IP Core. The DB-I2C IP Core targets systems-on-chip (SoC) ASSP, ASIC, and FPGA designs containing ARM embedded processors and the AMBA 2.0 APB on-chip bus, as well as other processors that support the APB bus.
The DB-I2C IP Core is offered in three versions:
| Model Number | Description |
| DB-I2C-MS-APB | Provides both Master and Slave function with optional parameterized FIFO for high performance designs. |
| DB-I2C-M-APB | Master only function with optional FIFO for smaller VLSI footprint. |
| DB-I2C-S-APB | Slave only function with optional FIFO or register bank with auto-increment addressing mode. |
Price and Availability
The DB9000AHB is available immediately in synthesizable Verilog or VHDL, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA).
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- CAST Ships I2C/SPI Controller IP Core for Easier Serial Communication
- Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.
- Production-proven CAN Controller IP Core, equipped with a Safety package (Safe DCAN-FD, ISO 26262: Safety manual, FMEDA), tailored specifically for High-End Automotive and Consumer Applications is available for immediate licensing
- LIN Controller IP Core, equipped with a Safety package (Safe LIN, ISO 26262: Safety manual, FMEDA), tailored specifically for High-End Automotive and Consumer Applications is available for immediate licensing
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack