Cadence adds VHDL model packager to Affirma

Cadence adds VHDL model packager to Affirma
By Michael Santarini, EE Times
January 4, 2000 (11:44 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000104S0018

SAN JOSE, Calif. — Targeting third-party intellectual-property developers, Cadence Design Systems Inc. has announced a VHDL companion to the Affirma model packager for Verilog that it released last April.

Cadence said the Affirma model packagers for VHDL and for Verilog form a complete packaging and simulation solution that resolves intellectual-property (IP) protection and distribution issues for system-on-chip design.

Introduction of the VHDL modeling tool brings Cadence up to par with Synopsys Inc., which last October launched its VHDL Model Compiler to match its Verilog Model Compiler.

John Willoughby, senior product marketing manager for verification products at Cadence, said that both of Cadence's model-packaging tools are based on the Affirma NC (native-compiled) single-kernel technology.

"We are using the same core technology for our simulators and mo del packaging — both Verilog and VHDL," said Willoughby. "This gives us a great performance advantage but it also ensures that your Verilog and VHDL models are going to act exactly alike."

The Affirma model packager uses the Affirma NC VHDL simulator to generate a protected VHDL simulation model that can be used in VHDL, Verilog or mixed-language simulations.

According to Cadence, the tool uses the NC compiler and elaborator to build a protected binary version of a VHDL design. It then packs the binary output with an NC engine and IEEE-1499 open-model interface (OMI) to make a complete model.

The OMI supports later connection with a simulator. If the simulator does not have an OMI socket, the Affirma model packager also supplies an IEEE-1364 programming-language interface-to-OMI adapter with each packaged model, allowing the system integrator to connect the model to a programming-language interface port.

Willoughby said this output to standard interfaces is an advantage over competing tools because it does not require model users to obtain a license, and Cadence doesn't charge fees for model distribution. Since models packaged with the Affirma model packager use standard interfaces, the tool does not require a license to run, he said.

However, if an IP author wants to generate a model that runs with any simulator besides an Affirma NC, he can buy an Affirma model packager export license, at a yearly subscription fee of $10,000.

The Affirma model packager is delivered to customers as part of the Affirma NC VHDL, NC Verilog and NC simulator products at no additional cost.