Cadence Solves VHDL IP Protection and Distribution Issues for SOC Design With New VHDL Model Packager

IP News

SAN JOSE, Calif.----Jan. 3, 2000-- Cadence Design Systems, Inc. , the world's leading supplier of electronic design products and services, today delivered a complete VHDL and Verilog® model packaging and simulation solution, resolving intellectual property (IP) protection and distribution issues for system-on-a-chip (SOC) design.

The Affirma(TM) model packager for VHDL provides high-performance, protected VHDL simulation models. Combined with the Affirma model packager for Verilog, released earlier this year, Cadence® now provides the most flexible IP packaging, distribution, and simulation support for both VHDL and Verilog models. Cadence charges no fees for model distribution and has based the Affirma model packager on industry-standard interfaces, increasing the accessibility and benefits of model packaging.

The new Affirma model packager for VHDL product is part of the Affirma NC (Native Compiled) simulator family, which uses the Cadence advanced simulation technology to provide the highest performance for packaged VHDL. Combined with the Affirma model packager for Verilog, this solution delivers the most complete mixed-language design support by using the same high-performance simulation technology to provide both Verilog and VHDL model packaging. In addition, models packaged with the Affirma model packager support the IEEE 1499 Open Model Interface (OMI) and the IEEE 1364 Programming Language Interface (PLI) standards for direct connection with a wide range of simulation environments including many popular VHDL and Verilog simulators.

``As systems get more complex, the need to leverage IP in a fast and cost-effective way is imperative,'' said Rahul Razdan, engineering vice president at Cadence. ``Our model packager solution for VHDL provides the industry's easiest, fastest, and most affordable way to create protected simulation models of VHDL designs. Based on industry-standard interfaces and Cadence's widely used advanced NC simulation technology the Affirma model packager dramatically enhances a designer's ability to create and share IP.''

The Affirma model packager uses the Affirma NC VHDL simulator to generate a high-performance, protected VHDL simulation model that can be used in VHDL, Verilog, or mixed-language simulations. The product uses the NC compiler and elaborator to build a protected binary version of a VHDL design. It then packs the binary output with an NC engine and OMI interface to make a complete model. The OMI interface supports later connection with a simulator. If the simulator does not have an OMI socket, the Affirma model packager also supplies a PLI to OMI adapter with each packaged model, allowing the system integrator to connect the model to a PLI port.

The Cadence Affirma NC VHDL product is a fully IEEE-standard compliant simulator that offers high-performance VHDL simulation, as well as supporting mixed-language design. It is founded upon second-generation native compiled technology from Cadence and uses the same Affirma SimVision debug environment deployed by the Affirma NC simulator and NC Verilog simulators.

Price and Availability

Models packaged with the Affirma model packager use standard interfaces and do not require a license to run. In an effort to support the use of shared IP, promote higher design productivity, and make viewing model packaging more accessible, Cadence does not charge extra for the use of shared IP provided by the Affirma model packager.

The Affirma model packager is delivered to customers as part of the Affirma NC VHDL, NC Verilog and NC simulator products at no additional cost. If the IP author wants to generate a model that runs with any simulator besides an Affirma NC simulator, they can purchase an Affirma model packager export license, which has a yearly subscription fee of $10,000 (U.S.). Cadence does not charge additional packaging or royalty fees for the OMI interface as it is a public standard.

About Cadence

Cadence Design Systems, Inc. is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.3 billion, Cadence is headquartered in San Jose, Calif. and has sales offices, design centers, and research facilities located around the world. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Note to Editors: Cadence, Verilog, and the Cadence logo are registered trademarks and Affirma is a trademark of Cadence Design Systems, Inc. All others are the properties of their holders.

     Cadence Design Systems, Inc.       Deborah Chalmers, 408/428-5795       debc@cadence.com