Maia EDA Launches New Automated Verification Tool

Maia designed to lead hardware engineers to effective module verification

CAMBRIDGE, England --December 10, 2009 -- Maia EDA has today announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initially being offered without cost by the company, allowing trial without registration or risk.

Maia is primarily targeted at hardware engineers who write and need to verify their own RTL code, but a key benefit of the tool is that it can be used by staff who have no knowledge of Verilog or VHDL, and who have only minimal programming skills. Modules and subsystems can be verified by anyone who has access to a specification, and who can construct sequences of vectors corresponding to the device inputs, and expected outputs.

“Module verification is normally carried out by the same hardware engineer who designed the module. The engineer is expected to hand over a working module,” commented Evan Lavelle, CTO of Maia EDA. “However, engineers are not usually programmers, and are unlikely to have the mindsets, or the time, which are required to create complex and exhaustive verification programs. The result is frequently that FPGAs are tested and debugged in-system, and ASIC developers have to buy complex system-level verification tools to find problems that should have been caught at a lower level. It's also a fact that most engineering companies don't have the resources to hire dedicated verification staff anyway. This is where Maia fits in.”

Maia automates the creation of testbenches by using declarative and fifth-generation language (5GL) techniques. An expected 'solution' is specified by listing sequences of inputs and expected outputs as vectors. Maia treats the vectors as constraints, and creates the corresponding self-checking testbench, automating the processes of driving and testing timed device inputs and outputs, clock and reset generation, stability checking, pipeline handling, internal signal probing and forcing, time handling, and error reporting.

Maia can be downloaded without charge from: http://maia-eda.net.

About Maia EDA

Maia EDA is a Cambridge-based EDA startup. The Maia language arose out of the need to create practical verification tools for real-world design, rather than esoteric system-level tools that have little or no relevance to working Electronic Engineers.The founders have extensive experience of the design and verification of ASIC and FPGA devices, as well as the development of complex compilers and toolchains for automated verification environments. The initial need was identified while carrying out hardware development, during which it was obvious that there was a disconnect between the needs of engineers and the available tools. This realisation led to the development of an automated testbench generator, which was constantly refined and tested on a large number of real designs, by real engineers, over several years. This proven technology has now been commercialised by Maia EDA.