Astera Labs and Alchip Announce Strategic Partnership to Advance Silicon Ecosystem for AI Rack-Scale Connectivity
Hyperscalers benefit from seamless integration of purpose-built compute and connectivity solutions to rapidly deploy AI infrastructure at scale
Santa Clara, Calif. and Taipei, Taiwan -- June 18, 2025 -- Astera Labs, a leading provider of purpose-built connectivity solutions for AI and cloud infrastructure, and Alchip Technologies, the high-performance ASIC leader, today announced a strategic partnership to advance the silicon ecosystem for next generation AI infrastructure. The collaboration combines Alchip’s custom ASIC development capabilities with Astera Labs’ comprehensive connectivity portfolio to deliver validated, interoperable solutions for hyperscalers building next-generation AI infrastructure.
“Our vision is to be the rack-level connectivity partner for hyperscalers,” said Sanjay Gajendra, president and chief operating officer, Astera Labs. “As custom compute platforms evolve to rack-scale implementations requiring advanced scale-up and scale-out connectivity, our partnership with Alchip will empower hyperscalers to seamlessly deploy complex AI infrastructure with a multitude of interconnect technologies, shorten time-to-market, and reduce integration risks.”
Hyperscalers face critical challenges in the AI infrastructure ecosystem as models scale to unprecedented sizes and complexity. Modern AI deployment requires rack-level solutions that integrate custom compute accelerators with high-performance connectivity fabrics, delivered within compressed development windows.
“The convergence of custom silicon and advanced connectivity is reshaping how AI infrastructure is architected and deployed,” said Johnny Shen, president and chief executive officer, Alchip Technologies. “Our collaboration with Astera Labs creates a powerful resource that will deliver complete solutions hyperscalers need to efficiently implement AI workloads at scale. Together, we’re streamlining purpose-built AI infrastructure that meets the performance and scale demands of next-generation applications.”
Hyperscalers will benefit from this strategic partnership with validated total solutions that combine Alchip’s ASIC design expertise and Astera Labs’ Intelligent Connectivity Platform which includes the COSMOS software suite. The partnership also advances industry innovation for next-generation AI connectivity standards including CXL®, Ethernet, NVLink Fusion, PCIe®, and UALink™, increasing options and strengthening the overall ecosystem.About Alchip
Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global High-Performance Computing and AI infrastructure ASIC provider of IC and packaging design, and production services for companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3D CoWoS packaging, chiplet design, and manufacturing management. Customers include global leaders in artificial intelligence, high-performance computing, supercomputing, mobile communications, entertainment device, networking equipment, and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).
About Astera Labs
Astera Labs advances next-generation AI infrastructure through purpose-built connectivity solutions to solve data, network, and memory bottlenecks at a rack-scale. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based solutions with the company’s COSMOS software suite to unify diverse components into cohesive, scalable systems with unprecedented rack-level observability and data center fleet management capabilities. By collaborating with hyperscalers, standards organizations, and partners, Astera Labs promotes a scalable AI infrastructure developed within open ecosystems and robust supply chains. Discover more at www.asteralabs.com.
Related Semiconductor IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- 1.8V/3.3V GPIO With I2C Compliant ODIO in GF 55nm
- Verification IP for UALink
Related News
- proteanTecs Enhances Astera Labs' Connectivity Solutions with Performance and Reliability Monitoring
- Elliptic Labs’ AI Platform Now Optimized for Ceva’s NeuPro-Nano NPU – Enabling Smarter Edge Devices
- Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry
- Marvell Develops Industry’s First 2nm Custom SRAM for Next-Generation AI Infrastructure Silicon
Latest News
- AiM Future and Franklin Wireless Sign MOU to Jointly Develop Lightweight AI Model and High-Efficiency 1 TOPS AI SoC Chipset
- GlobalFoundries and Silicon Labs Partner to Scale Industry-Leading Wi-Fi Connectivity
- GlobalFoundries Announces Availability of 22FDX+ RRAM Technology for Wireless Connectivity and AI Applications
- GlobalFoundries Announces Production Release of 130CBIC SiGe Platform for High-Performance Smart Mobile, Communication and Industrial Applications
- intoPIX Celebrates 20 Years of Innovation at IBC 2025