Actel drives up density of flash-based FPGAs
Actel drives up density of flash-based FPGAs
By Anthony Cataldo, EE Times
January 9, 2002 (5:07 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020109S0072
SUNNYVALE, Calif. Actel Corp. has unveiled a new family of flash-based field-programmable gate arrays (FPGAs) that the company says will give chip designers more reason to switch from ASICs to programmable logic. The ProASIC-Plus family, Actel's second generation of flash-based devices, contains from 150,000 to 1 million "system gates," or 40,000 to 300,000 ASIC gates. The amount of on-chip RAM bits has been doubled, and ranges from 36 kbits to 198 kbits. As for speed, the ProASIC-Plus family can go as high as 100 MHz. Though the speed of these flash-based devices may not be on par with SRAM-based FPGAs, Actel believes they have more of the attributes ASIC designers are looking for. Citing market research from Gartner Dataquest, the company figures that half of ASIC designs need less than 300,000 system gates, while 63 percent of all FPGA design starts run at less than 100 MHz. Moreover, 37 percent of programmable -logic devices are now used in volume production. Production-worthy PLDs should continue to grow as designers discover that the nonrecurring engineering cost of ASICs continues to balloon. "Paying $400,000 to $800,000 for ASIC NRE is not unusual," said Actel vice president of marketing Barry Marsh, who used to work for Fujitsu Microelectronics' ASIC division. If the new features of the Actel devices and the risk associated with designing an ASIC are not enough to sway designers to switch to an FPGA, then Actel is hoping the design environment will. ProASIC-Plus users do not need FPGA-specific tools at the front end of the design flow, but only for the back end when place and route come into play. Normally, FPGA designers need vendor-specific tools in both cases, according to Actel. "We give you a library that plugs into [Synopsys'] Design Compiler, which in turn plugs into an ASIC flow," Marsh said. Synthesis tools from Cadence, Exemplar, Model Technology and Synplicity could also be used, ac cording to Actel. Engineering samples of Actel's devices with 750,000 and 1 million system gates are now available for $199 and $399, respectively. The rest of the family should be ready for sampling in the second quarter. The smallest 150,000 system-gate device is expected to cost less than $20 in volume.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Actel Drives Low-Power Programmable Solutions into Asia Pacific with Extended Sales Network
- Actel Drives FPGAs "Under the Hood" Into Critical Automotive Powertrain and Safety Systems
- Actel Drives Industry's Lowest Power FPGAs into Portable Displays
- M31 high density and low power IP solutions on TSMC 55nm embedded flash technology
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers