Accellera Systems Initiative Announces SCE-MI 2.3
Updates give verification engineers more flexibility in their flows
Elk Grove, Calif., August 20, 2015 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on electronic design automation (EDA) and intellectual property (IP) standards, announced today updates to the Standard Co-Emulation Modeling Interface (SCE-MI).
The newest version of the standard, SCE-MI 2.3, expands the set of SCE-MI compliant DPI function argument data types, giving users less restrictions and more opportunity for design portability; extends the debug interface to provide C-side access to HDL-side registers, making the design on the emulator more accessible and debug easier; and adds a new mechanism that enables a SystemVerilog HVL-side testbench to call DPI functions to HDL-side SystemVerilog and vice versa, removing limitations in emulation usage.
“The goal of the SCE-MI standard is to reduce the effort necessary to get a system into an emulation or prototyping environment for verification,” stated Brian Bailey, Interface Working Group chair. “With the new updates, we are removing restrictions, improving emulation debug capabilities and providing an enhancement to overcome unintended language limitations, giving users more flexibility in their verification flows.”
The Interfaces Working Group is seeking input on SCE-MI 2.3 from the community for consideration in the next revision of the standard. To provide feedback on SCE-MI 2.3, please send email to sce-mi-feedback@lists.accellera.org. To download SCE-MI 2.3 for free, visit the Accellera Downloads page.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership.
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related News
- Accellera and Open SystemC Initiative Announce Plans to Unite
- Accellera and Open SystemC Initiative (OSCI) Approve Merger, Unite to Form Accellera Systems Initiative
- Accellera Systems Initiative Announces IEEE 1666 SystemC Language Standard for Electronic System-Level Design Is Available for Download at No Charge
- OCP-IP Announces Newly Enhanced Advanced Accellera Systems Initiative SystemC TLM Kit
Latest News
- SiMa.ai Raises $85M to Scale Physical AI, Bringing Total Funding to $355M
- Armv9 and CSS Royalties Drive Growth in $1bn Arm Q1 Earnings
- Creonic Releases DVB-S2X Demodulator Version 6.0 with Increased Bitwidth and Annex M Support
- Arm Q1 FYE26 Revenue Exceeds $1 Billion for Second Consecutive Quarter
- 1‑VIA Expands Globally with New India R&D Office in Pune to Accelerate Innovation in Data Center Connectivity