Cadence Innovus Implementation System Speeds Development of New Realtek DTV SoC Solution
2018-05-03 09:08:00
EDA & Design Tools
Chiplet News Archive - Page 505 of 1946
Aldec and Tamba Networks Release Ultra Low Latency Ethernet Solution for UltraScale+ FPGA at The Trading Show 2018
2018-05-03 08:59:00
SoC Architecture & Assembly
AI Gets New Benchmark
2018-05-03 04:42:00
Analysis & Insight
New MIPI I3C Host Controller Interface Speeds Sensor Integration
2018-05-02 15:27:00
Misc
New Arm IP Helps Protect IoT Devices from Increasingly Prevalent Physical Threats
2018-05-02 15:19:00
IP Cores & Design
Alliance Ventures and Definvest acquire stakes in Kalray
2018-05-02 13:23:00
Strategic Partnerships
TSMC's Roadmap Full, But Thin
2018-05-02 12:19:00
Analysis & Insight
Control of Arm's China business transferred to Chinese investors
2018-05-02 11:41:00
Analysis & Insight
Jim Keller Joins Intel to Lead Silicon Engineering
2018-05-02 11:29:00
People & Leadership
Global Semiconductor Sales Up 20 Percent Year-to-Year in Q1
2018-05-02 11:08:00
Analysis & Insight
Arm Physical IP to Accelerate Mainstream Mobile and IoT SoC Designs on TSMC 22nm ULP/ULL Platform
2018-05-02 09:46:00
IP Cores & Design
Samsung Electronics Partners with Avnet ASIC Israel to Strengthen Customer Support at the Forefront of ASIC Design Services
2018-05-02 09:28:00
Strategic Partnerships
Mentor enhances tool portfolio for TSMC 5nm FinFET and 7nm FinFET Plus processes and Wafer-on-Wafer stacking technology
2018-05-02 03:19:00
EDA & Design Tools
Imperas and Andes Extend Partnership, Delivering Models and Virtual Platforms for Andes RISC-V Cores with New AndeStar V5m Extensions
2018-05-01 18:44:00
EDA & Design Tools
Sondrel and NetSpeed Team Up to Deliver the Fastest, Lowest-risk Route to SoC Solutions
2018-05-01 18:19:00
Commercial Deals
Arteris FlexNoC Licensed by Canaan Creative for Artificial Intelligence ASICs
2018-05-01 18:07:00
Commercial Deals
New MIPS I7200 Processor Core Delivers Unmatched Performance and Efficiency For Advanced LTE/5G Communications And Networking IC Designs
2018-05-01 17:58:00
IP Cores & Design
Cadence Prototypes First IP Interface in Silicon for Preliminary Version of DDR5 Standard Being Developed in JEDEC
2018-05-01 17:51:00
IP Cores & Design
Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
2018-05-01 17:46:00
EDA & Design Tools
eSilicon deep learning ASIC in production qualification
2018-05-01 16:49:00
Commercial Deals