Maven Silicon is now an Approved Training Partner of Altera’s Solution Acceleration Partner (ASAP) Program
2025-06-25 05:30:00
Other
Recent News
Primemas Announces Customer Samples Milestone of World’s First CXL 3.0 SoC
2025-06-24 18:23:00
Chip
BrainChip and HaiLa Partner to Demonstrate Ultra-Low Power Edge AI Connectivity for IoT Sensor Applications
2025-06-24 13:22:00
Embedded Systems
Creonic's DVB-S2X/S2 IP Cores Now Support the New DVB-NIP Standard
2025-06-24 12:09:00
IP
Ceva Launches MotionEngine™ Hex: Bringing Precise, Touch-Free, Spatial Control to Smart TV, Gaming, and IoT Interfaces
2025-06-24 11:45:00
Embedded Systems
SEALSQ, ColibriTD, and Xdigit Announce Plan to Develop a Breakthrough Quantum Computing Based Solution Set to Revolutionize Semiconductor Wafer Yields for Sub-7nm Nodes
2025-06-24 11:39:00
Chip
Faraday Delivers Latest SerDes IP to Complete Interface Lineup on UMC’s 22nm Platform
2025-06-24 08:36:00
IP
Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025
2025-06-23 17:01:00
EDA
Yocto Project Welcomes RISC-V International as New Platinum Member, Expands Global Ecosystem and Leads with Cyber Resilience Act Preparedness
2025-06-23 15:45:00
Embedded Systems
Continental to Create an Advanced Electronics & Semiconductor Solutions Organization
2025-06-23 15:26:00
Business
Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
2025-06-23 13:02:00
EDA
Siemens turbocharges semiconductor and PCB design portfolio with generative and agentic AI
2025-06-23 12:55:00
EDA
Mirabilis Design Signs OEM Agreement with Cadence to Deliver VisualSim for System-Level Modeling and Performance Optimization
2025-06-23 11:32:00
EDA
Rapidus announces collaboration with Siemens for 2nm semiconductor design
2025-06-23 10:19:00
EDA
Caspia Technologies Collaboration to Enhance Security Verification in Siemens' Questa One With Caspia's Generative AI Security Platform
2025-06-23 10:07:00
EDA
True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL
2025-06-23 05:35:00
IP
True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
2025-06-20 06:26:00
Event
Launch of BrainChip Developer Hub Accelerates Event-Based AI Innovation on Akida™ Platform with Release of MetaTF 2.13
2025-06-20 05:54:00
Embedded Systems
Agnisys Ignites DAC 2025 with IDesignSpec Suite v9, IDS-FPGA Launch, AI² and IDS-Integrate Enhancements.
2025-06-19 15:36:00
EDA
CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
2025-06-19 08:09:00
IP
Primemas Announces Customer Samples Milestone of World’s First CXL 3.0 SoC
2025-06-24 18:23:00
Chip
BrainChip and HaiLa Partner to Demonstrate Ultra-Low Power Edge AI Connectivity for IoT Sensor Applications
2025-06-24 13:22:00
Embedded Systems
Creonic's DVB-S2X/S2 IP Cores Now Support the New DVB-NIP Standard
2025-06-24 12:09:00
IP
Ceva Launches MotionEngine™ Hex: Bringing Precise, Touch-Free, Spatial Control to Smart TV, Gaming, and IoT Interfaces
2025-06-24 11:45:00
Embedded Systems
SEALSQ, ColibriTD, and Xdigit Announce Plan to Develop a Breakthrough Quantum Computing Based Solution Set to Revolutionize Semiconductor Wafer Yields for Sub-7nm Nodes
2025-06-24 11:39:00
Chip
Faraday Delivers Latest SerDes IP to Complete Interface Lineup on UMC’s 22nm Platform
2025-06-24 08:36:00
IP
Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025
2025-06-23 17:01:00
EDA
Yocto Project Welcomes RISC-V International as New Platinum Member, Expands Global Ecosystem and Leads with Cyber Resilience Act Preparedness
2025-06-23 15:45:00
Embedded Systems
Continental to Create an Advanced Electronics & Semiconductor Solutions Organization
2025-06-23 15:26:00
Business
Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
2025-06-23 13:02:00
EDA
Siemens turbocharges semiconductor and PCB design portfolio with generative and agentic AI
2025-06-23 12:55:00
EDA
Mirabilis Design Signs OEM Agreement with Cadence to Deliver VisualSim for System-Level Modeling and Performance Optimization
2025-06-23 11:32:00
EDA
Rapidus announces collaboration with Siemens for 2nm semiconductor design
2025-06-23 10:19:00
EDA
Caspia Technologies Collaboration to Enhance Security Verification in Siemens' Questa One With Caspia's Generative AI Security Platform
2025-06-23 10:07:00
EDA
True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL
2025-06-23 05:35:00
IP
True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
2025-06-20 06:26:00
Event
Launch of BrainChip Developer Hub Accelerates Event-Based AI Innovation on Akida™ Platform with Release of MetaTF 2.13
2025-06-20 05:54:00
Embedded Systems
Agnisys Ignites DAC 2025 with IDesignSpec Suite v9, IDS-FPGA Launch, AI² and IDS-Integrate Enhancements.
2025-06-19 15:36:00
EDA
CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
2025-06-19 08:09:00
IP