Expedera’s Origin Evolution NPU IP Brings Generative AI to Edge Devices
2025-05-20 16:42:00
IP
Chiplet News Archive - Page 38 of 1929
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
2025-05-20 14:23:00
Embedded Systems
lowRISC Welcomes Javier Orensanz Martinez as CEO
2025-05-20 12:43:00
People
Cost-Optimized PolarFire® Core FPGAs and SoCs from Microchip Technology Deliver High Performance with a 30% Lower Price Tag
2025-05-20 11:24:00
FPGA
sureCore extends its sureFIT design service to include custom memory solutions for AI applications
2025-05-20 09:05:00
Business
BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit
2025-05-20 06:44:00
Event
SEMI Reports Typical Q1 2025 Semiconductor Seasonality with Potential for Atypical Shifts Due to Tariff Uncertainty
2025-05-19 15:04:00
Commentary / Analysis
Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition
2025-05-19 13:46:00
EDA
Alchip Among the First with NVIDIA NVLink Fusion Design Infrastructure
2025-05-19 12:50:00
Business
Marvell and NVIDIA to Provide Custom Solutions for Advanced AI Infrastructure
2025-05-19 12:46:00
Business
NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem
2025-05-19 10:24:00
Chip
InPsytech Joins Samsung SAFE™ IP Partner Program for Excellence in ONFI and UCIe IP Solutions
2025-05-19 07:32:00
Business
Digital Media Professionals (DMP) Unveils Next-Generation Edge AI SoC “Di1” Integrating Advanced AI Inference and Precision Real-Time 3D Ranging Engine
2025-05-19 06:54:00
Chip
How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
2025-05-17 04:39:00
Commentary / Analysis
Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
2025-05-16 16:54:00
Event
Automotive Industry Charts New Course with RISC-V
2025-05-16 14:01:00
Commentary / Analysis
Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
2025-05-16 12:36:00
Business
NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale
2025-05-16 12:22:00
Research
Flow Reaches Milestone: PPU Achieves End-to-End CPU Operations in Alpha Testing
2025-05-16 09:29:00
IP
Codasip: Toward Custom, Safe, Secure RISC-V Compute Cores
2025-05-15 19:48:00
Commentary / Analysis